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參數(shù)資料
| 型號： | MAX199BEWI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 8CH 28-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
5
Note 1:
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±4.096V input range.
Note 2:
External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3:
Ground “on” channel; sine wave applied to all “off” channels.
Note 4:
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5:
Guaranteed by design. Not tested.
Note 6:
Use static loads only.
Note 7:
Tested using internal reference.
Note 8:
PSRR measured at full-scale. VDD = 4.75V to 5.25V.
Note 9:
External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
(Note 13)
ns
70
CONDITIONS
tTR
RD High to Output Disable
ns
120
tINT1
RD Low to INT High Delay
ns
80
tCS
CS Pulse Width
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
80
tWR
WR Pulse Width
ns
0
tCSWS
ns
0
tCSWH
CS to WR Hold Time
CS to WR Setup Time
ns
0
tCSRS
ns
0
tCSRH
CS to RD Hold Time
CS to RD Setup Time
ns
100
tCWS
ns
50
tCWH
CLK to WR Hold Time
CLK to WR Setup Time
ns
60
tDS
ns
0
tDH
Data Valid to WR Hold
Data Valid to WR Setup
Figure 2, CL = 100pF (Note 12)
ns
120
tDO
ns
120
tDO1
HBEN High or HBEN Low to
Output Valid
RD Low to Output Data Valid
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