參數(shù)資料
型號(hào)： MAX3109ETJ+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 20/66頁(yè)
文件大?。?/td> 0K
描述： SEMICONDUCTOR OTHER
標(biāo)準(zhǔn)包裝： 60
系列： *
Dual Serial UART with 128-Word FIFOs
MAX3109
27
Maxim Integrated
Shutdown Mode
Drive the RST input to logic-low to enter shutdown mode.
Shutdown mode consumes less than 1FA. In shutdown
mode, all the MAX3109 circuitry is completely off. This
includes the I2C/SPI interface, the registers, the FIFOs,
and the clocking circuitry.
When the RST input transitions from low to high, the
MAX3109 exits shutdown mode and a hardware reset
is initiated. The chip initialization is complete when the
I2C/SPI controller is able to read out known register con-
tents from the MAX3109. This could, for example, be the
DIVLSB register.
The MAX3109 needs to be reprogrammed following a
shutdown.
Power-Up and IRQ
The IRQ output only operates when all supplies are
active. IRQ operates as a hardware active-low interrupt
output; IRQ is asserted when an interrupt is pending. An
IRQ interrupt is only possible during normal operation
if at least one of the interrupt enable bits in the IRQEn
register is set.
In polled mode, any register with a known reset value
can be polled to check whether the MAX3109 is ready for
operation. If the controller gets a valid response from the
polled register, then the MAX3109 is ready for operation.
Interrupt Structure
Figure 16 shows the structure of the interrupt. There are
four interrupt source registers: ISR, LSR, STSInt, and
SpclCharInt. The interrupt sources are divided into top-
level and low-level interrupts. The top-level interrupts
typically occur more often and can be read out by the
host controller directly through ISR. The low-level inter-
rupts typically occur less often and their specific source
can be read out by the host controller through LSR,
STSInt, or SpclCharInt. The three LSBs of ISR point to
the low-level interrupt registers that contain the details of
the interrupt source.
Interrupt Enabling
Every interrupt bit of the four interrupt registers can be
enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn, and STSIntEn registers. By default, all
interrupts are masked.
Interrupt Clearing
When an interrupt is pending (i.e., IRQ is asserted) and
ISR is read, both the ISR bits are cleared and the IRQ
output is deasserted. Low-level interrupt information
does not reassert IRQ for the same interrupt, but remains
stored in the low-level interrupt registers until each is
separately cleared. SpclCharInt and STSInt are clear-
on-read (COR). The LSR bits are only cleared when the
source of the interrupt is removed, not when LSR is read.
Figure 16. Simplified Interrupt Structure
0
IRQ1 IRQ0
GlobalIRQ
8
7
6
5
4
3
2
1
0
ISR
7
6
5
4
3
2
1
0
ISR
8
[1]
IRQ
[0]
LOW-LEVEL INTERRUPTS
TOP-LEVEL INTERRUPTS
7
6
5
4
3
2
1
0
SpclCharInt
8
7
6
5
4
3
2
1
0
STSInt
8
7
6
5
4
3
2
1
0
LSR
8
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