參數(shù)資料
型號： MAX3140EEI+
廠商： Maxim Integrated Products
文件頁數(shù)： 16/36頁
文件大小： 0K
描述： IC UART W/RS485 28-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 50
特點： 收發(fā)器
FIFO's： 8 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 4.75 V ~ 5.25 V
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 28-QSOP
供應(yīng)商設(shè)備封裝： 28-QSOP
包裝： 管件
MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
______________________________________________________________________________________
23
IRQ
N
RM MASK
TM MASK
PM MASK
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASK
R
S
Q
NEW DATA AVAILABLE
DATA READ
TRANSMIT BUFFER EMPTY
DATA READ
PE = 1 AND RECEIVED PARITY BIT = 1
PE = 0 OR RECEIVED PARITY BIT = 0
R
S
Q
R
S
Q
Figure 15. Functional Diagram for Interrupt Sources and Mask Blocks
Table 7. Interrupt Sources and Masks—Bit Descriptions
Transmit buffer is
empty
T
MEANING
WHEN SET
TM
The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted
low if TM = 1 and the transmit buffer becomes empty. This source is cleared on
the rising edge of SCLK‘s 16th pulse when using a READ DATA or WRITE DATA
operation. Although the interrupt is cleared, poll T to determine transmit-buffer
status.
DESCRIPTION
Received parity bit = 1
Transition on RX when
in shutdown; framing
error when not in
shutdown
RA/FE
RAM
This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3140 exits shutdown. IRQ is asserted
when RA is set and RAM = 1.
FE is determined solely by the currently received data, and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character. IRQ is asserted
when FE is set and RAM = 1.
MASK
BIT
Pr
PM
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0), or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value read by a READ DATA operation.
BIT
NAME
Data available
R
RM
The R bit is set when new data is available to be read or when data is being read
from the receive register/FIFO. FIFO is cleared when all data has been read. An
interrupt is asserted as long as R = 1 and RM = 1.
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MAX3140EEI+T 功能描述:UART 接口集成電路 SPI/uWire Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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