參數(shù)資料
型號(hào): MAX3140EEI+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/36頁(yè)
文件大?。?/td> 0K
描述: IC UART W/RS485 28-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
特點(diǎn): 收發(fā)器
FIFO's: 8 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 4.75 V ~ 5.25 V
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-QSOP
供應(yīng)商設(shè)備封裝: 28-QSOP
包裝: 管件
MAX3140
SCLK’s rising edge. DOUT (MISO) is read into the P
on SCLK’s rising edge. The first bit (bit 15) of DOUT
transitions on CS’s falling edge, and bits 14–0 transition
on SCLK’s falling edge. Figure 12 shows the detailed
serial timing specifications for the synchronous SPI
port.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on CS’s
rising edge. Every time CS goes low, a new 16-bit
stream is expected. Figure 13 shows an example of
using the WRITE CONFIGURATION register.
Table 1 describes the bits located in the WRITE CON-
FIGURATION, READ CONFIGURATION, WRITE DATA,
and READ DATA registers. This table also describes
whether the bit is a read or write bit and what the
power-on reset states (POR) of the bits are. Figure 14
shows an example of parity and word length control.
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
16
______________________________________________________________________________________
CS
SCLK
DIN
DOUT
tCSO
tCL
tDS
tDH
tDV
tCH
tDO
tTR
tCSH
tCS1
tCSS
Figure 12. Detailed Serial Timing Specifications for the Synchronous Port
1
CS
SCLK
DIN
DOUT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DATA
UPDATED
1
FEN
SHDN
TM
RM
PM
RAM
IR
ST
PE
L
B3
B2
B1
B0
RT
0
00
0
Figure 13. SPI Interface (Write Configuration)
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIME
D0
START
D1
D2
D3
D4
D5
D6
Pt
STOP
IDLE
PE = 1, L = 0
D0
START
D1
D2
D3
D4
D5
D6
D7
Pt
STOP
IDLE
PE = 0, L = 1
D0
START
D1
D2
D3
D4
D5
D6
STOP
IDLE
PE = 0, L = 0
D0
START
D1
D2
D3
D4
D5
D6
D7
STOP
IDLE
Figure 14. Parity and Word Length Control
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