參數(shù)資料
型號(hào)： MAX3140EEI
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 微控制器/微處理器
英文描述： CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMC PLUG; 50 OHM, RG400/U COAX, DOUBLE SHIELDED
中文描述： 1 CHANNEL(S), 240K bps, SERIAL COMM CONTROLLER, PDSO28
封裝： 0.150 INCH, 0.025 INCH PITCH, QSOP-28
文件頁數(shù)： 17/36頁
文件大小： 468K
代理商： MAX3140EEI
M
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
______________________________________________________________________________________
17
Table 1. Bit Descriptions
0
PE
POR
STATE
write
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt
bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to
be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3140 does not
calculate parity.
0
PE
read
Reads the value of the Parity-Enable bit.
0
PM
write
Mask for Pr bit.
IRQ
is asserted if
PM
= 1 and Pr = 1 (Table 7).
DESCRIPTION
0000
0000
X
Pr
read
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive
data (see the 9-Bit Networks section).
0
0
IR
read
Reads the value of the IR bit.
L
BIT
TYPE
write
B0–B3
write
Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
B0–B3
read
Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
BIT
NAME
Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1).
0
X
L
read
Reads the value of the L bit.
Pt
write
Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit net-
works, the MAX3140 does not calculate parity. If PE = 0, then this bit (Pt) is ignored in transmit
mode (see the 9-Bit Networks section).
00000000
0
D0r–D7r
read
Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is
always 0.
FEN
write
FIFO Enable. Enables the receive FIFO when
FEN
= 0. When
FEN
= 1, FIFO is disabled.
0
0
FEN
read
FIFO-Enable Readback.
FEN
’s state is read.
IR
write
Enables the IrDA timing mode when IR = 1.
No
change
XXXXXXXX
CTS
read
Clear-to-Send-Input. Records the state of the
CTS
pin (CTS bit = 0 implies
CTS
pin = logic
high).
D0t–D7t
write
Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.
0
PM
read
Reads the value of the
PM
bit (Table 7).
0
R
read
Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being
read from the receive register or FIFO. If performing a READ DATA or WRITE DATA operation,
the R bit will clear on the falling edge of SCLK's 16th pulse if no new data is available.
0
RM
write
Mask for R bit.
IRQ
is asserted if
RM
= 1 and R = 1 (Table 7).
0
RM
read
Reads the value of the
RM
bit (Table 7).
0
RAM
write
Mask for RA/FE bit.
IRQ
is asserted if
RAM
= 1 and RA/FE = 1 (Table 7).
0
RAM
read
Reads the value of the
RAM
bit (Table 7).
0
RTS
write
Request-to-Send Bit. Controls the state of the
RTS
output. This bit is reset on power-up (RTS
bit = 0 sets the
RTS
pin = logic high).
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