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參數(shù)資料
| 型號： | MAX3420EECJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC USB PERIPH CONTROLLER 32TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | USB 外設(shè)控制器 |
| 接口： | USB/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 15mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1407 (CN2011-ZH PDF) |
| 配用： | MAX3420EEVKIT-2+-ND - EVAL KIT FOR MAX3420E |
(NOVBUSIRQ)) and disconnect the internal 1.5k
Ω
pullup resistor. If the device using the MAX3420E is
bus powered (through a +3.3V regulator connected to
VCC), the MAX3420E VBCOMP input can be used as a
general-purpose input. Using VBCOMP as a general-
purpose input requires a 10k
Ω pullup resistor from
VBCOMP to VL. See the Applications Information sec-
tion for more details about this connection.
D+ and D-
The internal USB full-speed transceiver is brought out
to the bidirectional data pins D+ and D-. These pins are
±15kV ESD protected. Connect D+ and D- to a USB
“B” connector through 33
Ω ±1% series resistors. A
switchable 1.5k
Ω pullup resistor is internally connected
to D+. According to the USB rev 2.0 specification, a
self-powered peripheral must disconnect its 1.5k
Ω
pullup resistor to D+ in the event that the host turns off
bus power. The VBGATE bit in the USBCTL (R15) regis-
ter provides the option for the MAX3420E internal logic
to automatically disconnect the 1.5k
Ω resistor on D+.
The VBGATE and CONNECT bits of USBCTL (R15),
along
with
the
VBCOMP
comparator
output
(VBUS_DET), control the pullup resistor between VCC
and D+, as shown in Table 2. Note that if VBGATE = 1
and VBUS_DET = 0, the pullup resistor is disconnected
regardless of the CONNECT bit setting.
XI and XO
XI and XO connect an external 12MHz crystal to the
internal oscillator circuit. XI is the crystal oscillator
input, and XO is the crystal oscillator output. Connect
one side of an external 12MHz
±0.25% parallel reso-
nant crystal to XI, and connect XO to the other side.
Connect load capacitors (20pF max) to ground on both
XI and XO. XI can also be driven with an external
12MHz ±0.25% clock. If driving XI with an external
clock, leave XO unconnected. The external clock must
meet the voltage characteristics depicted in the
Electrical Characteristics table. Internal logic is single-
edge triggered. The external clock should have a nomi-
nal 50% duty cycle.
RES
Drive RES low to put the MAX3420E into a chip reset. A
chip reset sets all registers to their default states,
except for PINCTL (R17), USBCTL (R15), and SPI logic.
All FIFO contents are unknown during chip reset. Bring
the MAX3420E out of chip reset by driving RES high.
The RES pulse width can be as short as 200ns. See the
Device Reset section for a description of the resets
available on the MAX3420E.
INT
The MAX3420E INT output pin signals when a USB
event occurs that requires the attention of the SPI mas-
ter. The SPI master must set the IE bit in the CPUCTL
(R16) register to activate INT. When the IE bit is
cleared, INT is inactive (open for level mode, high for
negative edge, low for positive edge). INT is inactive
upon power-up or after a chip reset.
The INT pin can be a push-pull or open-drain output.
Set the INTLEVEL bit of the PINCTL (R17) register high
to program the INT output pin to be an active-low level
(open-drain output). An external pullup resistor to VL is
required for this setting. In level mode, the MAX3420E
drives INT low when any of the interrupt flags are set. If
multiple interrupts are pending, INT goes inactive only
when the SPI master clears the last active interrupt
request bit (Figure 10). The POSINT bit of the PINCTL
(R17) register has no effect on INT in level mode.
Clear the INTLEVEL bit to program INT to be an edge
(push-pull output). The active edge is programmable
using the POSINT bit of the PINCTL (R17) register. In
edge mode, the MAX3420E produces an edge refer-
enced to VL any time an interrupt request is activated,
or when an interrupt request is cleared and others are
USB Peripheral Controller
with SPI Interface
CLEAR
FIRST IRQ,
SECOND
IRQ STILL
ACTIVE
SECOND
IRQ
ACTIVE
FIRST IRQ
ACTIVE
CLEAR
IRQ
SINGLE
IRQ
,
INTLEVEL = 1
POSINT = X
INTLEVEL = 0
POSINT = 0
INTLEVEL = 0
POSINT = 1
CLEAR
LAST
PENDING
IRQ
(1) WIDTH DETERMINED BY TIME TAKEN TO CLEAR THE IRQ
(2) 10.67
μs
(1)
(2)
INT
Figure 10. Behavior of the INT Pin for Different INTLEVEL and
POSINT Bit Settings
Table 2. Internal Pullup Resistor Control
CONNECT
VBGATE
VBUS_DET
PULLUP
0
X
Not Connected
1
0
X
Connected
1
0
Not Connected
1
Connected
MAX3420E
Maxim Integrated
13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3420EECJ/V+ | 功能描述:外圍驅(qū)動器與原件 - PCI USB Peripheral Controller with SPI Interface RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3420EECJ/V+T | 功能描述:外圍驅(qū)動器與原件 - PCI USB Peripheral Controller with SPI Interface RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3420EECJ+ | 功能描述:外圍驅(qū)動器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3420EECJ+T | 功能描述:外圍驅(qū)動器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3420EECJ-T | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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