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參數(shù)資料
| 型號(hào)： | MAX3421EEHJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC USB PERIPH/HOST CNTRL 32TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 控制器類型： | USB 外設(shè)控制器 |
| 接口： | USB/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 15mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1407 (CN2011-ZH PDF) |
| 配用： | MAX3421EVKIT-1+-ND - EVAL KIT FOR MAX3421E |
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MAX3421E
USB Peripheral/Host Controller
with SPI Interface
23
Maxim Integrated
that the RESUME signal begins only after at least
5ms of the bus idle state. When the MAX3421E fin-
ishes its RESUME signaling, it sets the RWUDNIRQ
(remote wake-up done interrupt request) interrupt
flag in the USBIRQ (R13) register. At this time the
SPI master should clear the SIGRWU bit.
3) The host resumes bus activity. To enable the
MAX3421E to wake up from host signaling, the SPI
master sets the HOSCSTEN (host oscillator start
enable) bit of the USBCTL (R15) register. While in
this mode, if the MAX3421E detects a 1 to 0 transi-
tion on D+, the MAX3421E restarts the oscillator and
waits for it to stabilize.
Device Reset
The MAX3421E has three reset mechanisms:
Power-On Reset. This is the most inclusive reset
(sets all internal register bits to a known state).
Chip Reset. The SPI master can assert a chip
reset by setting the bit CHIPRES = 1, which has
the same effect as pulling the
RES pin low. This
reset clears only some register bits and leaves
others alone.
USB Bus Reset. A USB bus reset is the least
inclusive (clears the smallest number of bits).
Note: A power-on or chip reset clears the HOST bit and
puts the MAX3421E into peripheral mode.
Power-On Reset
At power-on, all register bits except 3 are cleared. The
following 3 bits are set to 1 to indicate that the IN FIFOs
are available for loading by the SPI master (BAV =
buffer available):
IN3BAVIRQ
IN2BAVIRQ
IN0BAVIRQ
Chip Reset
Pulling the
RES pin low or setting CHIPRES = 1 clears
most of the bits that control USB operation, but keeps
the SPI and pin-control bits unchanged so the interface
between the SPI master and the MAX3421E is not dis-
turbed. Specifically:
CHIPRES is unchanged. If the SPI master asserted
this reset by setting CHIPRES = 1, it removes the
reset by writing CHIPRES = 0.
CONNECT is unchanged, keeping the device
connected if CONNECT = 1.
General-purpose outputs GPOUT7–GPOUT0
are unchanged, preventing output glitches.
The GPX output selector (GPXB, GPXA) is
unchanged.
The bits that control the SPI interface are
unchanged: FDUPSPI, INTLEVEL, and POSINT.
The bits that control power-down and wakeup
behavior are unchanged: HOSCSTEN, PWRDOWN,
and SIGRWU.
All other bits except the three noted in the
Power-On
Reset section are cleared.
Note: The IRQ and IE bits are cleared using this reset.
This means that firmware routines that enable interrupts
should be called after a reset of this type. GPOUT7–
GPOUT0 are left unchanged during chip reset. They
are only cleared by an internal POR.
USB Bus Reset in Peripheral Mode
When the MAX3421E detects 21.33s of SE0, it asserts
the URESIRQ bit, and clears certain bits. This reset is
the least inclusive of the three resets. It maintains the
bit states listed in the
Power-On Reset and Chip Reset
sections, plus it leaves the following bits in their previ-
ous states:
EPFIFO registers are unchanged.
The GPOUT7–GPOUT0 bits are unchanged.
The IE bit is unchanged.
URESIE/IRQ and URESDNIE/IRQ are unchanged,
allowing the SPI master to check the state of USB
bus reset.
The EPFIFO registers are left in their pre-USB bus reset
states only for diagnostic purposes. Their values should
be considered invalid after a bus reset. The actual data
in the FIFOs is never cleared.
As with the chip reset, most of the interrupt request and
interrupt enable bits are cleared, meaning that the
device firmware must re-enable individual interrupts
after a bus reset. The exceptions are the interrupts
associated with the actual bus reset, allowing the SPI
master to detect the beginning and end of the host sig-
naling USB bus reset.
USB Bus Reset in Host Mode
As a host, an SPI master instructs the MAX3421E to
generate a USB bus reset by setting the BUSRST bit in
the HCTL register (R29). The MAX3421E generates the
correctly timed signal, and asserts the BUSEVENTIRQ
bit in the HIRQ register (R25) at completion.
Crystal Selection
The MAX3421E requires a crystal with the following
specifications:
Frequency: 12MHz
±0.25%
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| MAX3421EEHJ+ | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3421EEHJ+T | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3421EEHJ+TG2C | 制造商:Maxim Integrated Products 功能描述:USB PERIPHERAL/HOST CONTROLLER WITH SPI INTERFACE SPECIAL TA - Tape and Reel 制造商:Maxim Integrated Products 功能描述:USB PERIPHERAL/HOST CONTROLLER WITH SPI INTERFACE - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC USB PERIPH/HOST CNTRL TQFP 制造商:Maxim Integrated Products 功能描述:Peripheral Drivers & Components - PCIs USB Peripheral/Host Cntlr w/ SPI IF |
| MAX3421EETJ+ | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| MAX3421EETJ+T | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB Peripheral Controller w/SPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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