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參數(shù)資料
| 型號(hào)： | MAX3681EAG+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 1:4 DESERIALIZR W/LVDS 24SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 58 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 622Mbps |
| 輸入類(lèi)型： | LVDS |
| 輸出類(lèi)型： | LVDS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 4 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
MAX3681
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
NAME
FUNCTION
1, 2, 5, 8, 12
VCC
+3.3V Supply Voltage
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
PIN
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
11
SYNC-
Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
10
SYNC+
Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
9, 15, 22
GND
Ground
7
SCLK-
Inverting PECL Serial Clock Input
17, 19, 21, 24
PD0+ to PD3+
Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
16, 18, 20, 23
PD0- to PD3-
Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
14
PCLK+
Noninverting LVDS Parallel Clock Output
13
PCLK-
Inverting LVDS Parallel Clock Output
4-BIT
SHIFT
REGISTER
4-BIT
PARALLEL
OUTPUT
REGISTER
2-BIT
COUNTER
LVDS
PECL
LVDS
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SD+
SD-
SCLK+
SCLK-
SYNC+
SYNC-
100
Ω
MAX3681
Figure 1. Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3681EAG+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG-TG068 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3681EVKIT-SO | 功能描述:界面開(kāi)發(fā)工具 Evaluation Kit for the MAX3681 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
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