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參數(shù)資料
| 型號： | MAX3681EAG+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 1:4 DESERIALIZR W/LVDS 24SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 58 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 622Mbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 4 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 管件 |
MAX3681
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100
Ω differential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100
Ω of differential input
resistance, and therefore do not require external termi-
nation.
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50
Ω termination to (VCC - 2V)
when interfacing with a PECL source (see the
Alternative PECL Input Termination section).
__________Applications Information
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC - 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
6
_______________________________________________________________________________________
MAX3681
PECL
INPUTS
ZO = 50
Ω
ZO = 50
Ω
130
Ω
82
Ω
130
Ω
82
Ω
+3.3V
MAX3681
PECL
INPUTS
ZO = 50
Ω
50
Ω
ZO = 50
Ω
1.6k
2.7k
1.6k
2.7k
+3.3V
-2V
50
Ω
-2V
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
Figure 4. Alternative PECL Input Termination
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3681EAG+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3681EAG-TG068 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX3681EVKIT-SO | 功能描述:界面開發(fā)工具 Evaluation Kit for the MAX3681 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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