Detailed Description
Figure 1 is a functional diagram of the MAX3861 auto-
matic gain-control amplifier. The MAX3861 is divided
into three sections: main signal path, input signal
detection, and output signal detection.
Main Signal Path
The main signal path consists of variable gain ampli-
fiers with CML output levels and an offset-cancellation
loop. This configuration allows for overall gains from
-9.5dB to 43.5dB.
Offset-Cancellation Loop
The offset-cancellation loop partially reduces additional
offset at the input. In communications systems using
NRZ data with a 50% duty cycle, pulse-width distortion
present in the signal or generated by the transimped-
ance amplifier appears as input offset and is partially
removed by the offset-cancellation loop. An external
capacitor is required between CZ+ and CZ- to com-
pensate the offset-cancellation loop and determine the
lower 3dB frequency of the signal path.
Input Signal Detection and
SD Circuitry
The input signal detection circuitry consists of variable
gain amplifiers and threshold voltages. Input signal
detection information is compared to an internal refer-
ence and creates the RSSI voltage and an internal ref-
erence signal. The signal detect (SD) circuitry indicates
when the input signal is below the programmed thresh-
old by comparing a voltage proportional to the RSSI
signal with internally generated control voltages. The
SD threshold is set by a control voltage developed
across the external TH resistor (RTH). Two control volt-
ages, VASSERT and VDEASSERT, define the signal
detect assert and deassert levels. To prevent SD chat-
ter in the region of the programmed threshold, 2.8dB to
6.3dB of hysteresis is built into the SD assert/deassert
function. Thus, once asserted, SD is not deasserted
until sufficient gain is retained. When input signal
detection (SD and RSSI) is not required, connect EN to
a TTL low to power down this circuitry.
Output Signal Monitor and
Amplitude Control
Output amplitude typically can be adjusted from
400mVP-P to 920mVP-P by applying a control voltage
(0V to 2.0V) to the SC pin. See the Output Signal
Amplitude vs. SC Pin Voltage graph in the Typical
Operating Characteristics. Connect the VREF pin (2.0V)
to the SC pin for maximum output amplitude. The output
signal monitor pin provides a DC voltage linearly pro-
portional to the output signal.
Design Procedure
Program the SD Threshold
The SD threshold is programmed by an external resis-
tor, RTH, between the range of 2mVP-P to 100mVP-P.
The circuit is designed to have approximately 4.5dB of
hysteresis over the full range. See the Signal Detect
Threshold vs. RTH graph in the Typical Operating
Characteristics for proper sizing.
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
_______________________________________________________________________________________
7
VCC
MAIN SIGNAL PATH
CONTROL
BLOCK
AND
OUTPUT
SIGNAL
DETECT
INPUT
SIGNAL
DETECT
CZ+
CZ-
OUT+
OUT-
OSM
SC
VREF
SD
CG+
CG-
SD CIRCUITRY
GND
RTH
TH
EN
CD-
RSSI
CD+
IN-
IN+
MAX3861
Figure 1. Functional Diagram