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參數(shù)資料
| 型號： | MAX3872ETJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/AMP 32-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 60 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.67GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 托盤 - 晶粒 |
Loop Filter
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor (CFIL)
connected from FIL to VCC_VCO is required to set the
PLL damping ratio. Note that the PLL jitter bandwidth
does not change as the external capacitor changes,
but the jitter peaking, acquisition time, and loop stability
are affected. See the
Design Procedure section for
guidelines on selecting this capacitor.
VCOs with Programmable Dividers
The loop filter output controls the two on-chip VCOs.
The VCOs provide low phase noise and are trimmed to
the frequency of 2.488GHz and 2.667GHz. The RATE-
SET pin is used to select the appropriate VCO. The
VCO output is connected to programmable dividers
controlled by inputs RS1 and RS2. See Tables 2 and 3
for the proper settings.
LOL Monitor
The LOL output indicates a PLL lock failure, either
because of excessive jitter present at the data input or
because of loss of input data. The LOL output is asserted
low when the PLL loses lock.
DC-Offset Cancellation Loop
A DC-offset cancellation loop is implemented to remove
the DC offset of the limiting amplifier. To minimize the
low-frequency pattern-dependent jitter associated with
this DC-cancellation loop, the low-frequency cutoff is
10kHz (typ) with CAZ = 0.1F, connected from CAZ+ to
CAZ-. The DC-offset cancellation loop operates only
when threshold adjust is disabled.
Design Procedure
Decision Threshold Adjust
In applications in which the noise density is not bal-
anced between logical zeros and ones (i.e., optical
amplification using EDFA amplifiers), lower bit-error
ratios (BERs) can be achieved by adjusting the input
threshold. Varying the voltage at VCTRL from +0.3V to
+2.1V achieves a vertical decision threshold adjust-
ment of +170mV to -170mV, respectively (Figure 2).
Use the provided bandgap reference voltage output
(VREF) with a voltage-divider circuit or the output of a
DAC to set the voltage at VCTRL. VREF can be used to
generate the voltage for VCTRL (Figure 10). If threshold
adjust is not required, disable it by connecting VCTRL
directly to VCC and leave VREF floating.
Modes of Operation
The MAX3872 has three operational modes controlled
by the LREF and SIS inputs. The three operational
modes are normal, system loopback, and clock
holdover. Normal operation mode requires a serial data
stream at the SDI
± input, system loopback mode
requires a serial data stream at the SLBI
± input, and
clock holdover mode requires a reference clock signal
at the SLBI
± inputs. See Table 1 for the required LREF
and SIS settings. Once an operational mode is chosen,
the remaining logic inputs (RATESET, RS1, RS2, and
FREFSET) program the input data rate or reference
clock frequency.
Normal and System Loopback Settings
Three pins (RS1, RS2, and RATESET) are available for
setting the SDI
± and SLBI± input to receive the appropri-
ate data rate. The FREFSET pin can be set to a zero or 1
while in normal or system loopback mode (Table 2).
Clock Frequencies in Holdover Mode
Set the incoming reference clock frequency and outgoing
serial clock frequency by setting RS1, RS2, RATESET,
and FREFSET appropriately (Table 3).
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
_______________________________________________________________________________________
9
Table 1. Operational Modes
MODE
LREF
SIS
Normal
1
0
System loopback
1
Clock holdover
0
1 or 0
Table 2. Data Rate Settings
INPUT DATA RATE
(bps)
RS1
RS2
RATESET
FREFSET
2.667G
0
1
1 or 0
2.488G/2.5G
0
1 or 0
1.25G/1.244G
1
0
1 or 0
666.51M
0
1
1 or 0
622.08M
0
1
0
1 or 0
166.63M
1
0
1
1 or 0
155.52M
1
0
1 or 0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3872ETJ+ | 功能描述:計時器和支持產(chǎn)品 Multirate Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3872ETJ+T | 功能描述:計時器和支持產(chǎn)品 Multirate Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3872EVKIT | 功能描述:計時器和支持產(chǎn)品 Evaluation Kit for the MAX3872 MAX3874 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3873AEGP | 功能描述:計時器和支持產(chǎn)品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3873AEGP+ | 制造商:Maxim Integrated Products 功能描述:CLOCK RECOVERY 20QFN - Bulk |
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