參數(shù)資料
型號(hào): MAX3873AETP+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 0K
描述: IC RECOV/RETIME 2.5GBPS 20TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR)
PLL:
主要目的: SONET/SDH
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.67Gbps
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 20-TQFN-EP(4x4)
包裝: 管件
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
4
_______________________________________________________________________________________
Figure 1. Definition of Input Voltage Swing
Figure 2. Definition of Clock-to-Q Delay
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
800mV
VCC + 0.4V
VCC
VCC - 0.4V
VCC
VCC - 0.4V
VCC - 0.8V
SCLKO+
SDO
tCLK
tCLK-Q
Figure 4. Definition of LOL Assert Time and Frequency Acquisition Time
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL OUTPUT
LOL ASSERT TIME
Figure 3. Definition of Phase Acquisition Time
SERIAL DATA
1200 BITS OF 1–0 PATTERN
<2
μs
FASTRACK
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, CF = 0.022F, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, 2.488Gbps, TA = +25°C, unless otherwise
noted.) (Note 4)
Note 1: At TA = -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: CML outputs open.
Note 3: RL = 50
Ω to VCC.
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the falling edge of SCLKO+. See Figure 2.
Note 6: Measured with 223 - 1 PRBS.
Note 7: Jitter BW = 12kHz to 20MHz.
Note 8: RATESET = low.
Note 9: RATESET = high.
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