參數(shù)資料
型號: MAX3876
廠商: Maxim Integrated Products, Inc.
英文描述: 16-Channel LVDM Transceiver 64-TSSOP -40 to 85
中文描述: 2.5Gbps、低功耗、+3.3V時鐘恢復及數(shù)據(jù)再定時IC
文件頁數(shù): 6/12頁
文件大?。?/td> 744K
代理商: MAX3876
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on the rising edge of the data input
signal. Depending on the polarity of the frequency dif-
ference, the FD drives the VCO until the frequency dif-
ference is reduced to zero. Once frequency acquisition
is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
F
,
is required to set the PLL damping ratio. See
Design
Procedure
for guidelines on selecting this capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low-phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.5ps
RMS
within a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock (
LOL
) monitor is incorporated in the
MAX3876 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked,
LOL
switches to TTL high in approxi-
mately 800ns.
Note:
The
LOL
monitor is valid only when a data stream
is present on the inputs to the MAX3876. As a result,
LOL
does not detect a loss-of-power condition due to
loss of the incoming signal.
Design Procedure
Setting the Loop Filter
The MAX3876 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (f
L
) fixed at 1.5MHz. The external capacitor, C
F
,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer func-
tions.
The PLL zero frequency, f
Z
, is a function of external
capacitor C
F
, and can be approximated according to:
For an overdamped system (f
Z
/f
L
) < 0.25, the jitter peak-
ing (M
P
) of a second-order system can be approxi-
mated by:
For example, using C
F
= 0.1μF results in a jitter peaking
of 0.2dB. Reducing C
F
below 0.01μF may result in PLL
instability. The recommended value for C
F
is 1.0μF to
guarantee a maximum jitter peaking of less than 0.1dB.
C
F
must be a low TC, high-quality capacitor of type
X7R or better.
M
f
f
P
Z
L
=
20log 1+
f
( )
z
F
=
1
2
π
M
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
6
_______________________________________________________________________________________
C
F
= 1.0
μ
F
f
Z
= 2.6kHz
C
F
= 0.1
μ
F
f
Z
= 26kHz
H
O
(j2
π
f) (dB)
O
1000
f (kHz)
100
10
1
Figure 4. Open-Loop Transfer Function
C
F
= 1.0
μ
F
H(j2
π
f) (dB)
1000
100
10
1
f (kHz)
-3
0
C
C
F
= 0.1
μ
F
Figure 5. Closed-Loop Transfer Function
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MAX3877EHJ 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
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MAX3876EHJ-T 功能描述:時鐘發(fā)生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56