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參數(shù)資料
| 型號(hào)： | MAX3991UTG+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/AMP 24-TQFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH.XFP 光學(xué)接收器 |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 693.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 管件 |
MAX3991
Detailed Description
The MAX3991 clock and data recovery with limiting
amplifier restores data to XFI specifications. It consists of
a limiting amplifier with LOS power detector, and a PLL
data retimer with LOL indicator. An optional recovered
clock may also be enabled for performance testing.
Limiting Amplifier
The SDI inputs of the MAX3991 accept serial NRZ data
from the optical receiver assembly. The limiting amplifier
accepts signals as small as 7mVP-P and amplifies them
to allow recovery by the CDR. The limiting amplifier uses
an offset cancellation circuit to compensate for device
mismatch within the gain stages. The low-frequency cut-
off of the offset cancellation loop is typically 30kHz.
10Gbps Clock and Data Recovery
with Limiting Amplifier
8
_______________________________________________________________________________________
Figure 3. Functional Diagram
Functional Diagram
MAX3991
VTH
LIMITING
AMPLIFIER
VCO
DFF
DQ
CML
PHASE/
FREQUENCY
DETECTOR
LOL
DETECTOR
LOS
LOL
FUNCTIONAL
CONTROL
CFIL
CML
SDI+
SDI-
REFCLK+
REFCLK-
SDO+
SDO-
SCLKO+
SCLKO-
FCTL1
FCTL2
PLL
200
POL
Pin Description (continued)
PIN
NAME
FUNCTION
21
REFCLK+
Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the
reference clock source. REFCLK± have a 200
differential impedance. See the Detailed Description
section for more information. See Table 2.
22
REFCLK-
Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the
reference clock source. REFCLK± have a 200
differential impedance. See the Detailed Description
section for more information. See Table 2.
23
FCTL1
Function Control Input 1, TTL. See Table 3 for more information.
24
VTH
LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS
power detector can be disabled if VTH is connected to VCC, which forces LOS low.
EP
Exposed
Pad
Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal
and electrical performance. The MAX3991 uses exposed-pad variation T2444-4 in the package
outline drawing. See the exposed-pad package.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3991UTG+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 10Gbps Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3991UTG+T | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 10Gbps Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3992UTG+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 10Gbps Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3992UTG+T | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 10Gbps Clock & Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3996CGP | 功能描述:激光驅(qū)動(dòng)器 3-5.5V 2.5Gbps VCSEL & Laser Driver RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
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