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參數(shù)資料
| 型號： | MAX4031EEUD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP TRPL 144MHZ 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 通用 |
| 輸出類型： | 滿擺幅 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 144MHz |
| 轉(zhuǎn)換速率： | 115 V/µs |
| 電流 - 電源： | 12mA |
| 電流 - 輸出 / 通道： | 100mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
decrease bandwidth or cause oscillations. For exam-
ple, a noninverting gain-of-two configuration (RF = RG)
using 2k
resistors, combined with 4pF of amplifier
input capacitance and 1pF of PC board capacitance,
cause a pole at 79.6MHz. Since this pole is within the
amplifier bandwidth, it jeopardizes stability. Reducing
the 2k
resistors to 100 extends the pole frequency
to 1.59GHz, but could limit output swing by adding
200
in parallel with the amplifier’s load resistor
(Figures 1 and 2).
Layout and Power-Supply Bypassing
These amplifiers operate from a single 5V power sup-
ply. Bypass VCC to ground with a 0.1F capacitor as
close to VCC as possible. Maxim recommends using
microstrip and stripline techniques to obtain full band-
width. To ensure that the PC board does not degrade
the amplifier’s performance, design it for a frequency
greater than 1GHz. Pay careful attention to inputs and
outputs to avoid large parasitic capacitance. Under all
conditions observe the following design guidelines:
Do not use wire-wrap boards. Wire-wrap boards are
too inductive.
Do not use IC sockets. Sockets increase parasitic
capacitance and inductance.
Use surface mount instead of through-hole compo-
nents for better high-frequency performance.
Use a PC board with at least two layers. The PC
board should be as free from voids as possible.
Keep signal lines as short and as straight as possi-
ble. Do not make 90° turns; round all corners.
Output Capacitive Loading and Stability
The MAX4030E/MAX4031E are optimized for AC perfor-
mance and do not drive highly reactive loads, which
decreases phase margin and can produce excessive
ringing and oscillation. Figure 3 shows a circuit modifi-
cation that uses an isolation resistor (RISO) to eliminate
this problem. Figure 4 shows a graph of the Optimal
Isolation Resistor (RISO) vs. Capacitive Load. Figure 5
shows how a capacitive load causes excessive peak-
ing of the amplifier’s frequency response if the capaci-
tor is not isolated from the amplifier by a resistor. A
small isolation resistor (usually 10
to 15) placed
before the reactive load prevents ringing and oscilla-
tion. At higher capacitive loads, the interaction of the
load capacitance and the isolation resistor controls the
AC performance. Figure 6 shows the effect of a 10
isolation resistor on closed-loop response.
ESD Protection
As with all Maxim devices, ESD protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. Input and
output pins of the MAX4030E/MAX4031E have extra
protection against static electricity. Maxim’s engineers
have developed state-of-the-art structures enabling
these pins to withstand ESD up to ±15kV without dam-
age when placed in the test circuit (Figure 7). The
MAX4030E/MAX4031E are characterized for protection
to the following limits:
±15kV using the Human Body Model
±8kV using the Contact Discharge method speci-
fied in IEC 1000-4-2
±15kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2
MAX4030E/MAX4031E
Low-Cost, 144MHz, Dual/Triple Op Amps
with ±15kV ESD Protection
_______________________________________________________________________________________
7
IN
RG
VOUT = -(RF / RG) VIN
RF
VOUT_
MAX403_E
RL
150
Figure 2. Inverting Gain Configuration
IN_+
RG
VOUT = [1+ (RF / RG)] VIN_+
RF
VOUT_
MAX403_E
RL
150
Figure 1. Noninverting Gain Configuration
Figure 3. Driving a Capacitive Load Through an Isolation Resistor
RF
24
RISO
CL
VOUT_
VIN_+
MAX403_E
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