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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX4031EEUD+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OP AMP TRPL 144MHZ 14-TSSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鎳�(y墨ng)鐢細 | 閫氱敤 |
| 杓稿嚭椤炲瀷锛� | 婊挎摵骞� |
| 闆昏矾鏁�(sh霉)锛� | 3 |
| -3db甯跺锛� | 144MHz |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 115 V/µs |
| 闆绘祦 - 闆绘簮锛� | 12mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 100mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
decrease bandwidth or cause oscillations. For exam-
ple, a noninverting gain-of-two configuration (RF = RG)
using 2k
resistors, combined with 4pF of amplifier
input capacitance and 1pF of PC board capacitance,
cause a pole at 79.6MHz. Since this pole is within the
amplifier bandwidth, it jeopardizes stability. Reducing
the 2k
resistors to 100 extends the pole frequency
to 1.59GHz, but could limit output swing by adding
200
in parallel with the amplifier鈥檚 load resistor
(Figures 1 and 2).
Layout and Power-Supply Bypassing
These amplifiers operate from a single 5V power sup-
ply. Bypass VCC to ground with a 0.1F capacitor as
close to VCC as possible. Maxim recommends using
microstrip and stripline techniques to obtain full band-
width. To ensure that the PC board does not degrade
the amplifier鈥檚 performance, design it for a frequency
greater than 1GHz. Pay careful attention to inputs and
outputs to avoid large parasitic capacitance. Under all
conditions observe the following design guidelines:
Do not use wire-wrap boards. Wire-wrap boards are
too inductive.
Do not use IC sockets. Sockets increase parasitic
capacitance and inductance.
Use surface mount instead of through-hole compo-
nents for better high-frequency performance.
Use a PC board with at least two layers. The PC
board should be as free from voids as possible.
Keep signal lines as short and as straight as possi-
ble. Do not make 90掳 turns; round all corners.
Output Capacitive Loading and Stability
The MAX4030E/MAX4031E are optimized for AC perfor-
mance and do not drive highly reactive loads, which
decreases phase margin and can produce excessive
ringing and oscillation. Figure 3 shows a circuit modifi-
cation that uses an isolation resistor (RISO) to eliminate
this problem. Figure 4 shows a graph of the Optimal
Isolation Resistor (RISO) vs. Capacitive Load. Figure 5
shows how a capacitive load causes excessive peak-
ing of the amplifier鈥檚 frequency response if the capaci-
tor is not isolated from the amplifier by a resistor. A
small isolation resistor (usually 10
to 15) placed
before the reactive load prevents ringing and oscilla-
tion. At higher capacitive loads, the interaction of the
load capacitance and the isolation resistor controls the
AC performance. Figure 6 shows the effect of a 10
isolation resistor on closed-loop response.
ESD Protection
As with all Maxim devices, ESD protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. Input and
output pins of the MAX4030E/MAX4031E have extra
protection against static electricity. Maxim鈥檚 engineers
have developed state-of-the-art structures enabling
these pins to withstand ESD up to 卤15kV without dam-
age when placed in the test circuit (Figure 7). The
MAX4030E/MAX4031E are characterized for protection
to the following limits:
卤15kV using the Human Body Model
卤8kV using the Contact Discharge method speci-
fied in IEC 1000-4-2
卤15kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2
MAX4030E/MAX4031E
Low-Cost, 144MHz, Dual/Triple Op Amps
with 卤15kV ESD Protection
_______________________________________________________________________________________
7
IN
RG
VOUT = -(RF / RG) VIN
RF
VOUT_
MAX403_E
RL
150
Figure 2. Inverting Gain Configuration
IN_+
RG
VOUT = [1+ (RF / RG)] VIN_+
RF
VOUT_
MAX403_E
RL
150
Figure 1. Noninverting Gain Configuration
Figure 3. Driving a Capacitive Load Through an Isolation Resistor
RF
24
RISO
CL
VOUT_
VIN_+
MAX403_E
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-BNT-MU-F3 | CONVERTER MOD DC/DC 6.5V 200W |
| VI-J22-MZ-F4 | CONVERTER MOD DC/DC 15V 25W |
| VE-B2H-MX-F4 | CONVERTER MOD DC/DC 52V 75W |
| VE-B2H-MX-F3 | CONVERTER MOD DC/DC 52V 75W |
| VE-B2H-MX-F2 | CONVERTER MOD DC/DC 52V 75W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX4032 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:5V, 6dB Video Buffer with Sync-Tip Clamp, Output Sag Correction, and 150nA Shutdown Current |
| MAX4032ELT | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:5V 6DB VIDEO BUFFER W SYNC-TIP CLA - Rail/Tube |
| MAX4032ELT+ | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:5V 6DB VIDEO BUFFER W SYNC-TIP CLA - Rail/Tube |
| MAX4032ELT+T | 鍔熻兘鎻忚堪:瑕栭牷鏀惧ぇ鍣� 5V 6dB Video Buffer With Sync-Tip Clamp RoHS:鍚� 鍒堕€犲晢:ON Semiconductor 閫氶亾鏁�(sh霉)閲�:4 闆绘簮椤炲瀷: 宸ヤ綔闆绘簮闆诲:3.3 V, 5 V 闆绘簮闆绘祦: 鏈€灏忓伐浣滄韩搴�: 鏈€澶у伐浣滄韩搴�: 灏佽 / 绠遍珨:TSSOP-14 灏佽:Reel |
| MAX4032ELT-T | 鍔熻兘鎻忚堪:瑕栭牷鏀惧ぇ鍣� RoHS:鍚� 鍒堕€犲晢:ON Semiconductor 閫氶亾鏁�(sh霉)閲�:4 闆绘簮椤炲瀷: 宸ヤ綔闆绘簮闆诲:3.3 V, 5 V 闆绘簮闆绘祦: 鏈€灏忓伐浣滄韩搴�: 鏈€澶у伐浣滄韩搴�: 灏佽 / 绠遍珨:TSSOP-14 灏佽:Reel |
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