參數(shù)資料
型號(hào): MAX4032EUT+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 0K
描述: IC VIDEO BUFFER 6DB SOT23-6
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 緩沖器
電路數(shù): 1
-3db帶寬: 55MHz
轉(zhuǎn)換速率: 275 V/µs
電流 - 電源: 6.5mA
電流 - 輸出 / 通道: 85mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-6
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1423 (CN2011-ZH PDF)
其它名稱(chēng): MAX4032EUT+TDKR
MAX4032
5V, 6dB Video Buffer with Sync-Tip Clamp,
Output Sag Correction, and 150nA Shutdown Current
_______________________________________________________________________________________
3
Note 2: All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Voltage gain (AV) is referenced to the clamp voltage, i.e., an input voltage of VIN = VCLP + VI would produce an output volt-
age of VOUT = VCLP + AV x VI.
Note 4: Droop is guaranteed by the input bias current specification.
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V, GND = 0V, COUT = CSAG = 22F, CIN = 0.1F, RIN = 75
to GND, RL = 150 to GND, SHDN = 5.0V, TA = +25°C,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Small-Signal -3dB Bandwidth
BWSS
VOUT = 100mVP-P
55
MHz
Large-Signal -3dB Bandwidth
BWLS
VOUT = 2VP-P
45
MHz
Small-Signal 0.1dB Gain Flatness
BW0.1dBSS VOUT = 100mVP-P
18
MHz
Large-Signal 0.1dB Gain Flatness
BW0.1dBLS VOUT = 2VP-P
17
MHz
Slew Rate
SR
VOUT = 2V step
275
V/s
Settling Time to 0.1%
tS
VOUT = 2V step
25
ns
Power-Supply Rejection Ratio
PSRR
f = 100kHz
50
dB
Output Impedance
ZOUT
f = 5MHz
2.5
Differential Gain
DG
NTSC
0.4
%
Differential Phase
DP
NTSC
0.6
Degrees
Group Delay
D/dT
f = 3.58MHz or 4.43MHz
20
ns
Peak Signal to RMS Noise
SNR
VIN = 1VP-P, 10MHz BW
65
dB
Droop
CIN = 0.1F (Note 4)
2
3
%
SHDN Enable Time
tON
VIN = VCLP + 1V, SHDN = 5V, VOUT settled
to within 1% of the final voltage
250
ns
SHDN Disable Time
tOFF
VIN = VCLP + 1V, SHDN = 0V, VOUT settled
to below 1% of the output voltage
50
ns
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