參數(shù)資料
型號(hào): MAX4589EWP
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 0K
描述: IC MUX DUAL RF VIDEO 2CH 20-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 36
功能: 視頻多路復(fù)用器
電路: 2 x 2:1
導(dǎo)通狀態(tài)電阻: 60 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 12 V,± 2.7 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
MAX4589
Low-Voltage, High-Isolation,
Dual 2-Channel RF/Video Multiplexer
_______________________________________________________________________________________
3
VNO_ = 1VRMS, f = 10MHz,
Figure 5
VNO_ = 1VRMS, f = 10MHz,
all channels off, Figure 5
VNO_ = 3V, V+ = 5.5V,
V- = -5.5V, Figure 2
VCOM_ = 0, fIN = 1MHz, Figure 4
VNO_ = 3V, V+ = 4.5V,
V- = -4.5V, Figure 1
VNO_ = 3V, V+ = 4.5V,
V- = -4.5V, Figure 1
ISOURCE = -1mA
VNO_ = 0, fIN = 1MHz, Figure 4
CL = 1.0nF, VNO_ = 0,
RS = 0, Figure 3
CONDITIONS
dB
-70
VCT
Channel-to-Channel Crosstalk
dB
-74
VISO
Off-Isolation (Note 7)
pF
6
CCOM_(ON)
COM_ On-Capacitance
pF
4
CCOM_(OFF)
COM_ Off-Capacitance
pF
2
CNO_(OFF)
NO_ Off-Capacitance
pC
15
Q
Charge Injection
+25°C
ns
10
180
tBBM
Break-Before-Make Time Delay
(Note 3)
ns
150
300
tOFF
Turn-Off Time
ns
380
550
tON
Turn-On Time
V
VL - 1
VOH
DOUT Logic High Output
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
C, E
+25°C
C, E
+25°C
TA
ISINK = 3.2mA
V
0.4
VOL
DOUT Logic Low Output
C, E
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = VL = +4.5V to +5.5V, V- = -4.5V to -5.5V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical val-
ues are at TA = +25°C, V+ = VL = +5V, V- = -5V.) (Note 2)
C, E
600
350
Figure 5
MHz
200
BW
-3dB Bandwidth
+25°C
150
2-channel mode
4-channel mode
Figure 5
MHz
20
BW
-0.1dB Bandwidth
+25°C
15
4-channel mode
2-channel mode
Figure 6
ns
80
tDS
A_, EN to LE Rise Setup Time
C, E
Figure 6
ns
0
tDH
A_, EN to LE Rise Hold Time
C, E
Figure 6
ns
80
tL
LE Low Pulse Width
C, E
Figure 6
ns
80
tRS
RS Low Pulse Width
C, E
Figure 7
MHz
6.25
fCLK
Operating Frequency
C, E
Figure 7
ns
80
tCH
SCLK Pulse Width High
C, E
Figure 7
ns
80
tCL
SCLK Pulse Width Low
C, E
Figure 7
ns
60
tDS
DIN to SCLK Rise Setup Time
C, E
Figure 7
ns
0
tDH
DIN to SCLK Rise Hold Time
C, E
LOGIC OUTPUT (SERIAL INTERFACE)
PARALLEL-INTERFACE TIMING
SERIAL-INTERFACE TIMING
SWITCH DYNAMIC CHARACTERISTICS
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