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參數(shù)資料
| 型號(hào)： | MAX5109EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL NV 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5109
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5k
, CL = 100pF, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL TIMING (Figure 3, Note 8)
SCL Clock Frequency
fSCL
400
kHz
Setup Time for START Condition
tSU:STA
0.6
s
Hold Time for START Condition
tHD:STA
0.6
s
SCL High Time
tHIGH
0.6
s
SCL Low Time
tLOW
1.3
s
Data Setup Time
tSU:DAT
100
ns
Data Hold Time
tHD:DAT
0
0.9
s
SDA, SCL Rise Time
tR
300
ns
SDA, SCL Fall Time
tF
300
ns
Setup Time for STOP Condition
tSU:STO
0.6
s
Bus Free Time Between a STOP
and START Condition
tBUF
1.3
s
Pulse Width of Spike Suppressed
tSP
50
ns
Maximum Capacitive Load for
Each Bus Line
CB
(Note 9)
400
pF
Write NV Register Busy Time
(Note 10)
15
ms
NONVOLATILE MEMORY RELIABILITY
Data Retention
TA= +85°C50
Years
TA= +25°C
200,000
Endurance
TA= +85°C
50,000
Stores
Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.
Note 2: Guaranteed monotonic.
Note 3: Gain error is defined as:
where VF0,Meas is the DAC voltage with input code F0 hex and VF0,Ideal is the ideal DAC voltage with input code F0 hex or
(VREFH - VREFL) x (240 / 256) + VREFL.
Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +
0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.
Note 5: Output settling time is measured from the 50% point of the rising edge of the last SCL of the data byte to 0.5 LSB of OUT_’s
final value for a code transition from 10 hex to F0 hex.
Note 6: Crosstalk is defined as the coupling from a DAC switching from code 00 hex to code FF hex to any other DAC that is in a
steady state at code 00 hex.
Note 7: Reference feedthrough is defined as the coupling from one driven reference with input code = FF hex to any other DAC out-
put with the reference of the DAC at a constant value and input code = 00 hex.
Note 8: SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed
from a voltage level of (VIL + VIH) / 2.
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to
this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.
Note 10:The busy time begins from the initiation of the stop pulse.
256
00
×
()
,,
_
V
ZCE
V
F Meas
F Ideal
REFH
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