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參數(shù)資料
| 型號： | MAX5237EUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL 5V 10-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5236/MAX5237
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 10-Bit DACs
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS—MAX5236 (FIGURES 1 AND 2)
(VDD = +2.7V to +3.6V, GND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
74
ns
SCLK Pulse Width High
tCH
30
ns
SCLK Pulse Width Low
tCL
30
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
30
ns
DIN Hold Time
tDH
0ns
SCLK Rise to CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold Time
tCS1
30
ns
CS Pulse Width High
tCSW
75
ns
LDAC Pulse Width Low
tLDL
30
ns
CS Rise to LDAC Rise Hold Time
tCSLD
(Note 9)
75
ns
Note 1: Accuracy is guaranteed in the following way:
Note 2: Offset is measured at the code closest to 12mV.
Note 3: Gain from VREF_ to VOUT_ is typically 1.638 CODE/1024.
Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change
DAC B to full scale and measure
VOUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged.
DC crosstalk is the maximum
VOUT measured.
Note 5: The DAC output voltage is derived by gaining up VREF by 1.638 CODE/1024. This gain factor may cause VOUT to try to
exceed the supplies. The maximum value of VREF in the reference input range spec prevents this from happening at full
scale. The minimum VREF value of 0.25V is determined by linearity constraints, not DAC functionality.
Note 6: Accuracy is better than 1LSB for VOUT = 12mV to VDD - 180mV.
Note 7: Guaranteed by design. Not production tested.
Note 8: RLOAD =
∞ and digital inputs are at either VDD or GND. VOUT = full-scale output voltage.
Note 9: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents.
VDD
VREF_
ACCURACY GUARANTEED FROM CODE
TO CODE
3
1.250
6
1023
5
2.500
3
1023
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