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參數(shù)資料
| 型號： | MAX5237EUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 5V 10-UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 10µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5236/MAX5237
The general timing diagram of Figure 1 illustrates data
acquisition. Driving CS low enables the device to
receive data. Otherwise the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the control bits and D9–D6. The maxi-
mum clock frequency guaranteed for proper operation
is 13.5MHz. Figure 2 depicts a more detailed timing
diagram of the serial interface.
Power-Down and Shutdown Modes
As described in Tables 2 and 3, several serial interface
commands put one or both of the DACs into shutdown
mode. Shutdown modes are completely independent
for each DAC. In shutdown, the amplifier output
becomes high impedance, and OUT_ terminates to
GND through the 200k
(typ) gain resistors. Optionally
(see Tables 2 and 3), OUT_ can have an additional ter-
mination of 1k
to GND.
Full power-down mode shuts down the main bias gen-
erator and both DACs. The shutdown impedance of the
DAC outputs can still be controlled independently, as
described in Tables 2 and 3.
A serial interface command exits shutdown mode and
updates a DAC register. Each DAC can exit shutdown
at the same time or independently (see Tables 2 and
3). For example, if both DACs are shut down, updating
the DAC A register causes DAC A to power up, while
DAC B remains shutdown. In full power-down mode,
powering up either DAC also powers up the main bias
generator. To change from full power-down to both
DACs shutdown mode requires the waking of at least
one DAC between states.
When powering up the MAX5236/MAX5237 (powering
VDD) allow 60s (MAX5236) or 70s (MAX5237) for the
output to stabilize. When exiting full power-down mode,
allow 60s max (MAX5236) or 70s max (MAX5237) for
the output to stabilize. When exiting DAC shutdown
mode allow 50s max (MAX5236) or 60s max
(MAX5237) for the output to stabilize.
Load DAC Input (LDAC)
Asserting LDAC asynchronously loads the DAC regis-
ters from their corresponding input registers (DACs that
are shut down remain shut down). The LDAC input is
totally asynchronous and does not require any activity
on CS, SCLK, or DIN in order to take effect. If LDAC is
asserted coincident with a rising edge of CS, which
executes a serial command modifying the value of
either DAC input register, then LDAC must remain
asserted for at least 30ns following the CS rising edge.
This requirement applies only for serial commands that
modify the value of the DAC input registers.
Applications Information
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 6a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 6b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
Offset Error
The offset error (Figure 6c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Gain Error
Gain error (Figure 6d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding significantly reduce this noise,
but there is always some feedthrough caused by the
DAC itself.
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 10-Bit DACs
12
______________________________________________________________________________________
MSB
<----------- 16 bits of serial data -----------> LSB
3 Control Bits
MSB......10 Data Bits.....LSB
Sub-Bits
C2...C0
D9................................D0
S2……..S0
Table 1. Serial Data Format
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