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參數(shù)資料
| 型號： | MAX5316GTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/33頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SPI 24TQFN |
| 產(chǎn)品培訓模塊： | Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 3µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 2.29W |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x5） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
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27
MAX5316
16-Bit, ±1 LSB Accuracy Voltage Output
DAC with SPI Interface
Table 8b. Two’s Complement DIN Write Register (TC/SB) = 1) (0x1)
Table 9. General Configuration Write Register (0x4)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0x8000 when MZ = DGND (zero scale)
0x0000 when MZ = VDDIO (midscale)
BIT
NAME
DESCRIPTION
15:0
B[15:0]
16-bit DAC input code in two’s complement format. For clarity, a few examples are shown below.
1000 0000 0000 0000
0x8000
zero scale
1100 0000 0000 0000
0xC000
quarter scale
1111 1111 1111 1111
0xFFFF
midscale – 1 LSB
0000 0000 0000 0000
0x0000
midscale
0000 0000 0000 0001
0x0001
midscale + 1 LSB
0100 0000 0000 0000
0x4000
three-quarter scale
0111 1111 1111 1111
0x7FFF
full scale – 1 LSB
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
PD_SW
NO_HOLDEN
RST_SW
NO_BUSY
DOUT_ON
X
DEFAULT
0
1
0
X
BIT
NAME
DESCRIPTION
15
PD_SW
Software PD (Power-Down). Equivalent to the PD input.
0: Normal mode
1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor.
14
NO_HOLDEN
SPI Bus Hold Enable.
0: Bus hold enabled for SPI DOUT output. DOUT stays at its last value after the SPI CS
input rises at the end of the SPI frame (i.e. after the 24th clock cycle).
1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS
input rises at the end of the SPI frame (i.e. after the 24th clock cycle).
13
RST_SW
Software Reset. Equivalent to the RST input.
0: Place device in reset
1: Normal operation
Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low)
12
NO_BUSY
BUSY Input Disable.
0: BUSY input is active.
1: BUSY input is disabled.
Note that this does not affect the BUSY bit in the General Configuration and Status
Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally to
delay DAC updates.
11
DOUT_ON
SPI DOUT Output Disable. DOUT is disabled by default.
0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the
duration of the SPI frame.
1: DOUT output enabled.
10:0
—
Don’t care. These bits are reserved for the corresponding read command.
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