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參數(shù)資料
| 型號： | MAX5322EAI+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 10V SER 28SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準包裝： | 46 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1397 (CN2011-ZH PDF) |
where:
Bipolar output voltage:
where:
where VOUT_UNI is the unipolar output voltage, VOUT_BIP
is the bipolar output voltage, LSBUNI is the unipolar LSB
step size, LSBBIP is the bipolar LSB step size, VREF is
the reference voltage, and CODE is the decimal equiva-
lent of the binary, 12-bit, DAC input code.
In either case, a 000hex input code produces the mini-
mum output (-2 x VREF for bipolar and zero for unipo-
lar), an 800hex input code produces the midscale
output (zero for bipolar and VREF for unipolar), and a
FFFhex input code produces the full-scale output (2 x
VREF for bipolar and unipolar).
Output Amplifiers
The output-amplifier section can be configured as either
unipolar or bipolar by the UNI/BIP logic input. With
UNI/BIPA (UNI/BIPB) forced low, SW1 (SW4) and SW2
(SW5) in Figure 1 are closed, and SW3 (SW6) is open.
This configuration channels the DAC output through two
output stages to generate the ±2 x VREF output swing.
The first amplifier generates the ±VREF voltage range and
the second amplifier gains it up by two. When configured
for bipolar operation, the MAX5322 must be driven with
dual ±12V to ±15V power supplies.
With UNI/BIPA (UNI/BIPB) forced high, switches SW1
(SW4) and SW2 (SW5) are open and SW3 (SW6) is
closed. This configuration channels the DAC output
through only a single gain stage to generate a 0 to 2 x
VREF output swing.
Daisy-Chaining
SPI-/QSPI-/MICROWIRE-compatible devices can be
daisy-chained to reduce I/O lines from the host controller
(Figure 7). Daisy-chain devices by connecting the DOUT
of one device to the DIN of the next, and connect the
SCLK of all devices to a common clock. Data is shifted
out of DOUT 16.5 clock cycles after it is shifted into DIN,
and is available on the rising edge of the 17th clock
cycle. The SPI-/QSPI-/MICROWIRE-compatible serial
interface normally works at up to 10MHz, but must be
slowed to 6MHz if daisy-chaining. DOUT is high imped-
ance when CS is high.
Shutdown
Shutdown is controlled by software commands or by the
SHDN logic input. The SHDN logic input may be imple-
mented at any time. The SPI-/QSPI-/MICROWIRE-com-
patible serial interface remains fully functional, and the
device is programmable while shutdown. When shut
down, the MAX5322 supply current reduces to 2.8A
LSB
V
BIP
REF
=
×
4
2
12
V
LSB
CODE
V
OUT BIP
BIP
REF
_
(
) (
)
=×
×
2
LSB
V
UNI
REF
=
×
2
12
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________
15
RR
R
2R
D0
D11
D10
D1
REFA
AGND
0
10
1
OUTA
CONTROL LOGIC
2R
SGNDA
DAC REGISTER A
SW1
SW2
SW3
MAX5322
UNI/BIPA
Figure 4. Basic Inverted DAC Ladder
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