參數(shù)資料
型號(hào): MAX5532EUA+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 21/24頁(yè)
文件大小: 0K
描述: IC DAC 12BIT DUAL ULP 8-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 660µs
位數(shù): 12
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 471mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
MAX5532–MAX5535
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
6
_______________________________________________________________________________________
Note 1: Linearity is tested within codes 96 to 4080.
Note 2: Offset is tested at code 96.
Note 3: Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production tested.
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10k
Ω in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5532/MAX5534) or VREF = 3.9V (MAX5533/MAX5535).
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Serial Clock Frequency
fSCLK
010
MHz
DIN to SCLK Rise Setup Time
tDS
24
ns
DIN to SCLK Rise Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Pulse-Width High
tCSW
150
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Rise to CS Fall Setup
tCSO
0ns
CS Rise to SCK Rise Hold Time
tCS1
30
ns
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