The ground-sense input voltage range (" />
參數(shù)資料
型號(hào): MAX5774EVKIT+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/28頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL FOR MAX5774
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 32
位數(shù): 14
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 20µs
DAC 型: 電壓
工作溫度: 0°C ~ 85°C
已供物品:
已用 IC / 零件: MAX5774
MAX5773/MAX5774/MAX5775
be accessed as a pair (see Figure 3 for pairing of out-
put channels).
The ground-sense input voltage range (VGS1 or VGS2)
is -0.5V to +0.5V with respect to AGND. VGS is added
to the output voltage with unity gain. Ensure that the
resulting output voltage is within the valid output volt-
age range set by the power supplies. Refer to the
Output Amplifiers (OUT0–OUT31) section for the effect
of the ground-sense inputs on the DAC outputs.
Offset DAC
The MAX5773/MAX5774/MAX5775 feature an offset
DAC that determines the output voltage range. While
each device provides an allowable output voltage
range, the offset DAC determines the endpoint voltages
of the range. Table 1 shows the offset DAC code nec-
essary for each device’s output-voltage range.
The MAX5773/MAX5774/MAX5775 offset DAC can be
programmed with any of the three output voltage ranges.
The specifications in the
Electrical Characteristics table
are only guaranteed (production tested) for the offset
code associated with each particular part number.
The offset DAC is summed with the GS_ input voltage
(see the
Functional Diagram). Any change in the offset
DAC affects all 32 DACs.
The offset DAC is also double buffered with an input
and DAC register.
Software commands for the MAC-bypass for all chan-
nels and load-DAC for all channels do not affect the off-
set DAC.
The data format for writing to the offset DAC is: control
bits C3–C0 = 0011, address bits A5–A0 = 110000, 14
data bits (and S1, S0), and 6 don’t-care bits as shown
in Table 2.
Output Amplifiers (OUT0–OUT31)
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and
glitch suppression for the DAC outputs. The output
buffers slew at 1V/s and can drive 10k
in parallel
with 100pF. The output buffers are powered by AVCC
and VSS. AVCC and VSS determine the maximum output
voltage range of the device.
The input code, the voltage reference, the offset DAC
output, the voltage on GS1 (or GS2), and the gain of the
output amplifier determine the output voltage. Calculate
VOUT as follows:
V
GAIN V
DAC CODE OFFSET DAC CODE
V
OUT
REF
GS
=
××
+
()
_
2
14
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
16
______________________________________________________________________________________
OUT_
±0.5 LSB
tS
tLDAC
LDAC
Figure 2. LDAC Timing
CONTROL
BITS
ADDRESS
BITS
DATA BITS
DON’T-CARE
BITS
C3–C0
A5–A0
D13–D0 and
S1, S0*
6 Don’t-Care
Bits
0011
110000
See Table 1
XXXXXX
Table 2. Offset DAC Input Data Format
*
S1 = S0 = 0 for proper 14-bit operation.
CONTROL
BITS
ADDRESS
BITS
DATA BITS
DON’T-CARE
BITS
C3–C0
A5–A0
D13–D0 and
S1, S0*
6 Don’t-Care
Bits
0010
111111
XXXXXXXXXX
XXXX00
XXXXXX
Table 3. Software Load-DAC Input Data
Format
*
S1 = S0 = 0 for proper 14-bit operation.
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