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參數(shù)資料
| 型號： | MAX5821MEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DL 2WIRE SER 8-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5821
The next command word writes to the power-down reg-
isters (Figure 7). Setting bits A or B to 1 sets that DAC
to the selected power-down mode based on the states
of PD0 and PD1 (Table 1). Any combination of the
DACs can be controlled with a single write sequence.
Read Data Format
In read mode (R/W = 1), the MAX5821 writes the con-
tents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5821. The device transmits the first byte of
data, waits for the master to acknowledge, then trans-
mits the second byte. Figure 8 shows an example-read
data sequence.
I2C Compatibility
The MAX5821 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typi-
cal I2C application. The communication protocol sup-
ports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5821 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5821 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5821 2-wire digital interface is I2C/SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces, such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass VDD with a 0.1F capacitor to
ground as close to the device as possible.
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
10
______________________________________________________________________________________
S
MSB
A6
A5
A4
A3
A2
A1
A0
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
P
ACK
LSB
MSB
LSB
EXAMPLE-WRITE DATA SEQUENCE
EXAMPLE-WRITE TO POWER-DOWN REGISTER SEQUENCE
LSB
S
MSB
A6
A5
A4
A3
A2
A1
A0
C3
C2
C1
C0
D9
D8
D7
D6
XXX
X
B
A
PD1
PD0
P
ACK
LSB
MSB
LSB
R/W
Figure 6. Example-Write Command Sequences
XX
XXBA
PD1
PD0
Figure 7. Extended Command Byte Format
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