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參數(shù)資料
| 型號(hào)： | MAX5875EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 200MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 14ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
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MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________
11
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5875.
Clock Inputs (CLKP, CLKN)
The MAX5875 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AVCLK) to achieve the optimum jitter performance.
Drive the differential clock inputs from a single-ended
or a differential clock source. For single-ended opera-
tion, drive CLKP with a logic source and bypass CLKN
to GND with a 0.1F capacitor.
CLKP and CLKN are internally biased to AVCLK / 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is > 5k
.
Data Timing Relationship
Figure 4 displays the timing relationship between digital
CMOS data, clock, and output signals. The MAX5875
features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propa-
gation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN and OUTIP/OUTIN
(OUTQP/OUTQN) when operating in single-port (inter-
leaved) mode. In dual-port (parallel) mode, the clock
latency is 5.5 clock cycles for both channels. Table 2
shows the DAC output codes.
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB,
DORI)
The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logic-
high level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary
input format.
The DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set DORI high to configure
the MAX5875 as a dual-port DAC. Set DORI low to con-
figure the MAX5875 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
CMOS DAC Inputs (A15/B15–A0/B0, XOR, SELIQ)
The MAX5875 latches input data on the rising edge of the
clock in a user-selectable two’s-complement or binary
format. A logic-high voltage on TORB selects two’s-
complement and a logic-low selects offset binary format.
OUTIP
OUTIN
1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
RSET
IREF
10k
DACREF
1
F
IREF = VREFIO / RSET
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
Table 2. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET BINARY
TWO’S
COMPLEMENT
OUT_P
OUT_N
0000 0000 0000 0000 1000 0000 0000 0000
0
IOUTFS
0111 1111 1111 1111 0000 0000 0000 0000 IOUTFS / 2 IOUTFS / 2
1111 1111 1111 1111 0111 1111 1111 1111
IOUTFS
0
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