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參數(shù)資料
| 型號(hào)： | MAX5875EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 200MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 14ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________
13
consumption from 22.5mA to less than 2A and the
analog current consumption from 78mA to less than
3A. Set PD high to power down the MAX5875. Set PD
low for normal operation.
When powered down, the power consumption of the
MAX5875 is reduced to less than 14W. The MAX5875
requires 10ms to wake up from power-down and enter a
fully operational state. The PD integrated pulldown resistor
activates the MAX5875 if PD is left floating.
Applications Information
CLK Interface
The MAX5875 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AVCLK) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5psRMS for meeting the speci-
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1F capacitor.
Figure 5 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP/Agilent 8644B signal generator) and a wide-
band transformer. Alternatively, these inputs may be dri-
ven from a CMOS-compatible clock source; however, it
is recommended to use sinewave or AC-coupled differ-
ential ECL/PECL drive for best dynamic performance.
Differential-to-Single-Ended Conversion
Using a Wideband RF Transformer
Use a pair of transformers (Figure 6) or a differential
amplifier configuration to convert the differential voltage
existing between OUTIP/OUTQP and OUTIN/OUTQN to
a single-ended voltage. Optimize the dynamic perfor-
mance by using a differential transformer-coupled out-
put to limit the output power to < 0dBm full scale. Pay
close attention to the transformer core saturation char-
acteristics when selecting a transformer for the
MAX5875. Transformer core saturation can introduce
strong 2nd-order harmonic distortion, especially at low
output frequencies and high signal amplitudes. For best
results, center tap the transformer to ground. When not
using a transformer, terminate each DAC output to
ground with a 25
resistor. Additionally, place a 50
resistor between the outputs (Figure 7).
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
GND
1:1
25
25
CLKP
CLKN
TO DAC
0.1
F
0.1
F
Figure 5. Differential Clock-Signal Generation
MAX5875
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
T1, 1:1
T2, 1:1
GND
50
100
50
VOUT, SINGLE-ENDED
Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer
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