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參數(shù)資料
| 型號： | MAX6499ATA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC CTLR PROT SW 8-TDFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 電壓 - 工作： | 72V |
| 技術(shù)： | 混合技術(shù) |
| 功率（瓦特）： | 1.45W |
| 電路數(shù)： | 1 |
| 應(yīng)用： | 通用 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN-EP（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MAX6499ATA+TDKR |
MAX6495–MAX6499
72V, Overvoltage-Protection Switches/
Limiter Controllers with an External MOSFET
6
Maxim Integrated
Pin Description
PIN
MAX6495
MAX6496
MAX6497/MAX6498
MAX6499
NAME
FUNCTION
11
1
IN
Positive Supply Voltage. Connect IN to the positive side of the input voltage. Bypass IN
with a 10F capacitor to GND.
22
2
SHDN
Shutdown Input. Drive
SHDN low to force GATE low and turn off the external n-channel
MOSFET. Drive
SHDN low and then high to reset the overvoltage-condition latch. SHDN
is internally pulled to GND with 1A of current. Connect
SHDN to IN for normal operation.
33
3
OVSET
Overvoltage-Threshold Adjustment Input. Connect OVSET to an external resistive
voltage-divider network to adjust the desired overvoltage-disable or overvoltage-limit
threshold. Connect the resistor network to the input side (drain) of the n-channel
MOSFET for overvoltage switch turn-off applications or to the output side (source) of the
n-channel MOSFET for overvoltage-limiting applications (MAX6495/MAX6496/MAX6499).
4
5
GND
Ground
5
6
GATE
Gate-Driver Output. Connect GATE to the gate of the external n-channel MOSFET switch.
GATE is the output of a charge pump with a 100A pullup current to 10V (typ) above IN
during normal operation. GATE is quickly clamped to OUTFB during an overvoltage
condition. GATE pulls low when
SHDN is low.
67
7
OUTFB
Output-Voltage-Sense Input. Connect OUTFB to the source of the external n-channel
MOSFET switch.
—
4
—
GATEP
p-Channel Gate-Driver Output. Connect GATEP to the gate of an external p-channel
MOSFET to provide low-drop reverse-voltage protection. GATEP is biased to ensure that
the p-channel MOSFET is on during normal operating modes, the gate-to-source is not
overstressed during load-dump/overvoltage conditions, and the p-channel MOSFET is
off during reverse-battery conditions.
—
8
——
N.C.
No Connection. Not internally connected.
—
4
—
POK
Power-OK Output. POK is an open-drain output. POK remains low while POKSET is
below the internal POKSET threshold. POK goes high impedance when POKSET goes
above the internal POKSET threshold. Connect POK to an external pullup resistor.
—
8
—
POKSET
Power-OK Threshold-Adjustment Input. POK remains low while POKSET is below the
internal POKSET threshold (1.18V). POK goes high impedance when POKSET goes
above the internal POKSET threshold (1.24V). Connect a resistive divider from OUTFB
to POKSET to adjust the desired undervoltage threshold.
—
——
4
CLEAR
Latch Clear Input. Connect
CLEAR to a logic-high to latch the device off after an
overvoltage condition. With OVSET below VTH, pulse CLEAR low (5s typ)
to reset the output latch. Connect
CLEAR to GND to make the latch transparent.
—
——
8
UVSET
Undervoltage-Threshold Adjustment Input. Connect UVSET to an external resistive
voltage-divider network to adjust the desired undervoltage threshold.
—
——
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to
provide a low thermal-resistance path from the IC junction to the PC board. Do not use
as the primary electrical connection to GND.
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