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參數(shù)資料
| 型號(hào)： | MAX649 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Eval Board for ISL6527 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | 5V/3.3V/3V或可調(diào)、高效率、低IQ、降壓型DC-DC控制器 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 261K |
| 代理商： | MAX649 |
MAX6443–MAX6452
P Reset Circuits with Long Manual Reset
Setup Period
_______________________________________________________________________________________
3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MR2 Minimum Setup Period
Pulse Width
MAX6447/MAX6448/MAX6451/MAX6452
1
s
MR2 Glitch Rejection
MAX6447/MAX6448/MAX6451/MAX6452
100
ns
MR2 to RESET Delay
MAX6447/MAX6448/MAX6451/MAX6452
200
ns
Manual Reset Timeout Period
tMRP
140
210
280
ms
MR1 to VCC Pullup Impedance
25
50
75
k
MR2 to VCC Pullup Impedance
MAX6445/MAX6446/MAX6449/MAX6450
25
50
75
k
VCC
≥ 1.00V, ISINK = 50A, RESET asserted
0.3
VCC
≥ 1.20V, ISINK = 100A, RESET
asserted
0.3
VCC
≥ 2.55V, ISINK = 1.2mA, RESET
asserted
0.3
RESET Output Low
(Open Drain or Push-Pull)
VOL
VCC
≥ 4.25V, ISINK = 3.2mA, RESET
asserted
0.4
V
VCC
≥ 1.80V, ISOURCE = 200A, RESET
deasserted
0.8
× VCC
VCC
≥ 3.15V, ISOURCE = 500A, RESET
deasserted
0.8
× VCC
RESET Output High
(Push-Pull)
VOH
VCC
≥ 4.75V, ISOURCE = 800A, RESET
deasserted
0.8
× VCC
V
RESET Open-Drain Leakage
Current
ILKG
RESET deasserted
1
A
MR1, MR2, MR2
Input Low Voltage
VIL
0.3
× VCC
V
MR1, MR2, MR2
Input High Voltage
VIH
0.7
× VCC
V
Note 1: Devices production tested at +25°C. Overtemperature limits are guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.0V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1)
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