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參數(shù)資料
| 型號： | MAX6621AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSLATOR PECI-I2C 10-MSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
The result is a 16-bit word (low byte transmitted first,
high byte second) that contains the register that
caused ALERT to assert. An error (8103h) is returned
when there is no active ALERT.
RESET
The MAX6621 features a power-on reset (POR), bus
lockout reset, and a reset input (RESET). The power-on
reset monitors VCC and holds all outputs in high imped-
ance until VCC passes the POR threshold. The
MAX6621 monitors VCC for brownout conditions even
after power-up.
Bus Lockout Timeout Reset
If an I2C transaction starts and gets locked up for
greater than 20ms, the MAX6621 asserts the internal
bus lockup reset that restarts itself in the default startup
condition.
RESET Input
The MAX6621 features a RESET input that allows users
to directly reset to the default startup conditions. Pull
RESET low for a minimum of 10ns for a valid reset. The
MAX6621 requires 100μs to be accessible after RESET
has been asserted.
Version Information Command
Table 18 shows the command to read the firmware version.
The result is a 16-bit word (low byte transmitted first,
high byte second), e.g., 0100h for the MAX6621 firmware
version 1.0.
Serial Interface
The MAX6621 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire inter-
face. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master and slave. A master (typically
a microcontroller) initiates all data transfers to and from
the MAX6621 and generates the SCL clock that syn-
chronizes the data transfer (Figure 5).
The MAX6621 SCL and SDA lines operate as both
inputs and open-drain outputs. A pullup resistor is
required on SCL and SDA.
Each transmission consists of a START condition sent
by a master, followed by the MAX6621 7-bit slave
address, plus an R/W bit, one or more data bytes, and
finally a STOP condition (Figure 6). To write to a
MAX6621 register, a write transmission consists of a
START condition, followed by the MAX6621 7-bit slave
address plus R/W = 0, a register address byte, one
data byte, and finally a STOP condition. To read from a
MAX6621 register, a combined write and read trans-
missions are required. The first write transmission con-
sists of a START condition, followed by the MAX6621
7-bit slave address plus R/W = 0, a register address
byte, and finally a STOP condition that sets the register
to be read. The second read transmission consists of a
START condition, followed by the MAX6621 7-bit slave
address plus R/W = 1, one or more data bytes, and
finally a STOP condition that reads the data from the
MAX6621
PECI-to-I2C Translator
______________________________________________________________________________________
13
COMMAND
DESCRIPTION
TYPE
RESULT
09h
Get firmware
version
ReadWord
16 bit word
Table 18. Firmware Command
SDA
SCL
tHD, STA
tR
tHIGH
tSU, DAT
tLOW
tF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tHD, DAT
tSU, STO
tSU, STA
tHD, STA
tBUF
Figure 5. 2-Wire Serial-Interface Timing Details
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