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參數(shù)資料
| 型號： | MAX6621AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSLATOR PECI-I2C 10-MSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
MAX6621
specified register. These write and read transmissions
can be joined using a repeated START even though the
MAX6621 7-bit slave address needs to be present pre-
ceding the R/W bits.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 6).
Data Transfer and Acknowledge
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 7).
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so that the SDA line is stable
low during the high period of the clock pulse. When the
master is transmitting to the MAX6621, the MAX6621
generates the acknowledge bit because the MAX6621
is the recipient. When the MAX6621 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX6621 has a 7-bit long slave address (Figure 9).
The 8th bit following the 7-bit slave address is the R/W
bit. The R/W bit is low for a write command and high for
a read command.
PECI-to-I2C Translator
14
______________________________________________________________________________________
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
Figure 6. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 7. Bit Transfer
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGEMENT
START
CONDITION
SDA BY
RECEIVER
12
89
S
Figure 8. Acknowledge
0
1
A2
A1
A0
ACK
0
SDA
SCL
Figure 9. Slave Address
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