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參數(shù)資料
| 型號： | MAX6917EO50 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDSO20 |
| 封裝： | 0.150 INCH, 0.025 INCH PITCH, MO-137AD, QSOP-20 |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 349K |
| 代理商： | MAX6917EO50 |
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MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
22
______________________________________________________________________________________
Crystal-Fail Detect
The crystal-fail detect circuit looks for a loss of oscillation
from the 32.768kHz oscillator for 30 cycles (typ) or more.
Both the control register and the status register are used
in the crystal-failure detection scheme (Table 1).
The crystal-fail detect circuit sets the XTAL FAIL bit in
the status register to one for a crystal failure and to zero
for normal operation. Once the status register is read,
the XTAL FAIL bit is reset to zero, if it was previously
one. If the crystal-fail-detect circuit continues to sense
a failed crystal, then the XTAL FAIL bit is set again.
On initial power-up, the crystal-fail detect circuit is
enabled. Since it takes a while for the low-power,
32.768kHz oscillator to start, the XTAL FAIL bit in the
status register can be set to one indicating a crystal
failure. The XTAL FAIL bit should be polled a number of
times to see if it is set to zero for successive polls. If the
polling is far enough apart, a few polled results could
guarantee that a maximum of 10s had elapsed since
power-on, at which time the oscillator would be consid-
ered truly failed if the XTAL FAIL bit remains one.
On subsequent power-ups, when XTAL EN is set to
one, if XTAL FAIL is set to one, time data should be
considered suspect.
The crystal-fail-detection circuit functions in both VCC
and VBATT modes when the XTAL EN bit is set in the
control register.
Manual Reset Input
A logic low on MR asserts RESET. RESET remains
asserted while MR is low, and for tRP after it returns
high (Figure 10). MR has an internal pullup resistor, so
it can be left open if it is not used. Internal debounce
circuitry requires a minimum low time on the MR input
of 1s with 35ns maximum glitch immunity.
Reset Output
A P’s reset input starts the P in a known state. The
MAX6917’s P supervisory circuit asserts a reset to
prevent code-execution errors during power-up, power-
down, and brownout conditions. The RESET output is
guaranteed to be active for 0V < VCC < VRST, provided
VBATT is greater than VBATT (min). If VCC drops below
and then exceeds the reset threshold, an internal timer
keeps RESET active for the reset timeout period tRP;
after this interval, RESET becomes inactive high. This
condition occurs at either power-up or after a VCC
brownout.
The RESET output is also activated when the watchdog
interrupt function is enabled but no transition is detect-
ed on the WDI input. In this case, RESET is active for
the period tRP before becoming inactive again. When
RESET is active, all inputs—WDI, MR, CE_IN, SDA, and
SCL—are disabled.
The MAX6917EO30 is optimized to monitor 3.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 2.7V (3.0V - 10%), but is
guaranteed to occur before the power supply falls
below 2.5V (3.0V - 15%).
The MAX6917EO33 is optimized to monitor 3.3V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 3.0V (3.0V is just above
3.3V - 10%), but is guaranteed to occur before the
power supply falls below 2.8V (3.3V - 15%).
The MAX6917EO50 is optimized to monitor 5.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 4.5V (5.0V - 10%), but is
guaranteed to occur before the power supply falls
below 4.1V (4.1V is just below 5.0V - 15%).
Negative-Going VCC Transients
The MAX6917 is relatively immune to short-duration nega-
tive transients (glitches) while issuing resets to the P dur-
ing power-up, power-down, and brownout conditions.
Therefore, resetting the P when VCC experiences only
small glitches is usually not recommended. Typically, a
VCC transient that goes 150mV below the reset threshold
and lasts for 90s or less does not cause a reset pulse to
be issued. A 0.1F capacitor mounted close to the VCC
pin provides additional transient immunity.
MR
CE OUT
CE IN
RESET
tRCE
tRP
Figure 10. Manual-Reset Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX6917EO30 | REAL TIME CLOCK, PDSO20 |
| MAX6917EO33 | REAL TIME CLOCK, PDSO20 |
| MAX8893AEWV+ | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA30 |
| MAX8893BEWV+ | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA30 |
| MAX8893CEWV+ | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA30 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX6917EO50+ | 功能描述:實(shí)時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| MAX6917EO50+T | 功能描述:實(shí)時時鐘 Integrated Circuits (ICs) RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| MAX691AC/D | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX691ACPE | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX691ACPE+ | 功能描述:監(jiān)控電路 MPU Supervisor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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