參數(shù)資料
型號: MAX6917EO50
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: REAL TIME CLOCK, PDSO20
封裝: 0.150 INCH, 0.025 INCH PITCH, MO-137AD, QSOP-20
文件頁數(shù): 3/31頁
文件大?。?/td> 349K
代理商: MAX6917EO50
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
______________________________________________________________________________________
11
Detailed Description
Functional Description
The MAX6917 contains eight 8-bit timekeeping registers,
seven 8-bit alarm threshold registers, one status register,
one control register, one alarm-configuration register, and
96 x 8 bits of SRAM. In addition to single-byte reads and
writes to registers and RAM, there is a burst timekeeping
register read/write command, a burst RAM read/write
command, and a battery-test command that allows soft-
ware-commanded testing of the backup battery at any
time. An I2C-bus-compatible interface allows serial com-
munication with a P. When VCC is less than the reset
threshold, the serial interface is disabled to prevent erro-
neous data from being written to the MAX6917. A P
supervisory section and an NVRAM controller are provid-
ed for ease of implementation with P-based systems. A
crystal fail-detect circuit and a data-valid bit can be used
to guarantee RAM data integrity and valid timekeeping
data. Two reference frequencies outputs, 32.768kHz and
1Hz, are provided for external device clocking. Time and
calendar data are stored in a binary-coded decimal
(BCD) format. Figure 1 shows the functional diagram of
the MAX6917.
Real-Time Clock
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the months is
automatically adjusted for months with fewer than 31
days, including corrections for leap years through 2099.
Crystal Oscillator
The MAX6917 uses an external, standard 6pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscil-
lator start time is dependent mainly upon applied VCC
and ambient temperature. The MAX6917, because of
its low timekeeping current, exhibits a typical startup
time of 1s to 2s.
I2C-Compatible Interface
The I2C bus allows bidirectional, 2-wire communication
between different ICs. The two lines are serial data line
(SDA) and serial clock line (SCL). Both lines must be
connected to a positive supply through individual
pullup resistors (see the Typical Application Circuit).
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). Figure 2 shows a
timing diagram for I2C communication.
Pin Description (continued)
PIN
NAME
FUNCTION
11
32KHZ
32.768kHz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
12
1HZ
1Hz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
13
SDA
Open-Drain Data Input/Output. I2C bus serial data input/output connection.
14
SCL
Serial Clock Input. I2C bus clock for input/output data transfers.
15
ALM
Open-Drain, Active-Low Alarm Output. ALM goes low when RTC time matches alarm thresholds set in
the alarm threshold registers. ALM stays low until cleared by reading or writing to the alarm configuration
register or to any of the alarm threshold registers.
16
CE_OUT
Chip-Enable Output. CE_OUT goes low only when CE_IN is low and RESET is not asserted. If CE_IN is
low when RESET is asserted, CE_OUT remains low for tRCE or until CE_IN goes high, whichever occurs
first. CE_OUT is pulled to VOUT.
17
BATT_LO
Open-Drain, Battery-Low Indicator. BATT_LO is active low when the VBATT input is tested below VBTP if
the internal trip is selected in the control register (POR default). If external trip is selected in the control
register, then BATT_LO is active low when TRIP is less than VTRIP.
18
RESET
Open-Drain, Active-Low Reset Output. RESET pulses low for tRP when triggered, and stays low
whenever VCC is below the reset threshold or when MR is logic low. RESET remains low for tRP after
either VCC rises above the reset threshold or MR goes from low to high.
19
VCC
Main Supply Input. Connect a 0.1F bypass capacitor from VCC to GND.
20
VBATT
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, VOUT switches from VCC to
VBATT. When VCC rises above VBATT or the reset threshold, VOUT reconnects to VCC. VBATT may exceed
VCC. Connect VBATT to GND if no backup-battery supply is used. Connect a 0.1F low-leakage bypass
capacitor from VBATT to GND.
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