參數(shù)資料
型號(hào): MAX691A
廠商: Maxim Integrated Products, Inc.
英文描述: Microprocessor Supervisory Circuits(帶看門狗復(fù)位、片選和支持備用電池的復(fù)位器)
中文描述: 微處理器監(jiān)控電路
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 164K
代理商: MAX691A
M
Mic roproc essor S upervisory Circ uits
14
______________________________________________________________________________________
parator. Select the ratio of R1 and R2 such that PFI sees
1.25V when V
falls to the desired trip point (V
).
Resistor R3 adds hysteresis. It will typically be an order
of magnitude greater than R1 or R2. The current
through R1 and R2 should be at least 1μA to ensure that
the 25nA (max) PFI input current does not shift the trip
to prevent it from
point. R3 should be larger than 10k
al noise rejection.
Monitoring a Negative V oltage
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 12’s circuit. When
ative supply voltage drops, –——Ogoes high. This cir-
cuit’s accuracy is affected by the PFI threshold
tolerance, the V
CC
voltage, and resistors R1 and R2.
Bac kup-Battery Replac ement
The backup battery may be disconnected while V
is
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
Negative-Going V
CC
T ransients
While issuing resets to the μP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration, negative-going V
transients (glitches). It is usually undesirable to reset
the μP when V
CC
experiences only small glitches.
Figure 7 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are
not
generated. The graph was produced using negative-
going V
pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset com-
parator overdrive). The graph shows the maximum
pulse width a negative-going V
transient may typical-
ly have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V
transient that
goes 100mV below the reset threshold and lasts for
40μs or less will not cause a reset pulse to be issued.
A 100nF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
Connec ting a T iming Capac itor at OS C IN
When OSC SEL is connected to ground, OSC IN dis-
connects from its internal 10μA (typ) pull-up and is
internally connected to a ±100nA current source.
When a capacitor is connected from OSC IN to ground
(to select alternative reset and watchdog timeout peri-
ods), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
reset and watchdog timeout period. To prevent timing
errors or oscillator start-up problems, minimize external
current leakage sources at this pin, and locate the
capacitor as close to OSC IN as possible. The sum of
PC-board leakage + OSC capacitor leakage must be
small compared to ±100nA.
100
0
10
1000
10000
40
20
80
60
M
RESET COMPARATOR OVERDRIVE,
(Reset Threshold Voltage - V
CC
) (mV)
M
μ
s
100
V
CC
= 5V
T
A
= +25°C
0.1
μ
F CAPACITOR
FROM V
OUT
TOGND
Figure 13. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
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