receives data through an I
參數(shù)資料
型號(hào): MAX7314AEG+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 24/25頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
接口: I²C
輸入/輸出數(shù): 18
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 管件
MAX7314
Serial Interface
Serial Addressing
The MAX7314 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7314 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7314 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k
Ω,
is required on the SDA. The MAX7314 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7k
Ω,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7314
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7314, the device gen-
erates the acknowledge bit because the MAX7314 is
the recipient. When the MAX7314 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX7314 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
8
_______________________________________________________________________________________
Figure 3. Start and Stop Conditions
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 4. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 5. Acknowledge
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGE
START
CONDITION
SDA BY
RECEIVER
12
89
S
Figure 6. Slave Address
SDA
SCL
1
MSB
LSB
ACK
00
A6
0
A2
R/W
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