參數資料
型號: MAX7314AEG+
廠商: Maxim Integrated Products
文件頁數: 25/25頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24QSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
接口: I²C
輸入/輸出數: 18
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 24-QSOP
包裝: 管件
The second (A5), third (A4), fourth (A3), sixth (A1), and
last (A0) bits of the MAX7314 slave address are always
1, 0, 0, 0, and 0. Slave address bits A6 and A2 are
selected by the address input AD0. AD0 can be con-
nected to GND, V+, SDA, or SCL. The MAX7314 has four
possible slave addresses (Table 1), and therefore a
maximum of four MAX7314 devices can be controlled
independently from the same interface.
Message Format for Writing the MAX7314
A write to the MAX7314 comprises the transmission of
the MAX7314’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX7314
is to be written to by the next byte, if received (Table 2).
If a STOP condition is detected after the command byte
is received, then the MAX7314 takes no further action
beyond storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7314 selected by the command byte (Figure
8). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7314 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 registers or blink phase 1 registers) is given in
Figure 10.
MAX7314
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
_______________________________________________________________________________________
9
Table 1. MAX7314 Address Map
DEVICE ADDRESS
PIN AD0
A6
A5
A4
A3
A2
A1
A0
SCL
1
100
000
SDA
1
100
GND
0
100
000
V+
0
100
Figure 8. Command and Single Data Byte Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
1
BYTE
AUTOINCREMENT MEMORY ADDRESS
D15 D14 D13 D12 D11 D10
D9
D8
D1
D0
D3
D2
D5
D4
D7
D6
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7314's REGISTERS
R/W
Figure 9. n Data Bytes Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
N
BYTES
AUTOINCREMENT MEMORY ADDRESS
D15 D14 D13 D12 D11 D10
D9
D8
D1
D0
D3
D2
D5
D4
D7
D6
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7314's REGISTERS
R/W
Figure 7. Command Byte Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
ACKNOWLEDGE FROM MAX7314
D15
D14
D13
D12
D11
D10
D9
D8
COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
ACKNOWLEDGE FROM MAX7314
R/W
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