參數(shù)資料
型號: MAX7317ATE+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/12頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER SPI 10B 16TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接口: SPI/Microwire
輸入/輸出數(shù): 10
中斷輸出:
電源電壓: 2.25 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(3x3)
包裝: 帶卷 (TR)
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SCLK
V+
DIN
DOUT
P9
P8
P7
P6
P5
TOP VIEW
MAX7317AEE
QSOP
CS
P0
P3
P1
P2
P4
GND
Applications Information
Hot Insertion
The I/O ports P0–P9 remain high impedance with up to
8V asserted on them when the MAX7317 is powered
down (V+ = 0V). The MAX7317 can therefore be used
in hot-swap applications.
SPI Routing Considerations
The MAX7317’s SPI interface is guaranteed to operate
at 26Mbps on a 2.5V supply, and on a 3.3V supply typi-
cally operates at 35Mbps. This means that transmission
line issues should be considered when the interface
connections are longer than 100mm, particularly with
higher supply voltages. Avoid running long adjacent
tracks for SCLK, DIN, and CS without interleaving GND
traces; otherwise, the signals may cross-couple, giving
false clock or chip-select transitions. Ringing may man-
ifest itself as communication issues, often intermittent,
typically due to double clocking caused by ringing at
the SCLK input. Fit a 1k
to 10k parallel termination
resistor to either GND or V+ at the DIN, SCLK, and CS
inputs to damp ringing for moderately long interface
runs. Use line-impedance-matching terminations when
making connections between boards.
Output-Level Translation
The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
than the MAX7317 supply. An external pullup resistor
can be used on any output to convert the high-imped-
ance logic-high condition to a positive voltage level.
The resistor can be connected to any voltage up to 7V.
When using a pullup on a constant-current output,
select the resistor value to sink no more than a few hun-
dred A in logic-low condition. This ensures that the
current sink output saturates close to GND. For inter-
facing CMOS inputs, a pullup resistor value of 220k
is
a good starting point. Use a lower resistance to
improve noise immunity in applications where power
consumption is less critical, or where a faster rise time
is needed for a given capacitive load.
Power-Supply Considerations
The MAX7317 operates with a power-supply voltage of
2.25V to 3.6V. Bypass the power supply to GND with a
0.047F ceramic capacitor as close to the device as
possible. For the QFN version, connect the underside
exposed pad to GND.
Chip Information
TRANSISTOR COUNT: 14,865
PROCESS: BiCMOS
.
N-15
N-31
N-30
N-29
N-28
N-27
N-26
N-25
N-24
N-23
N-22
N-21
N-20
N-19
N-18
N-17
N-16
BIT
1
BIT
2
N-14
N-13
N-12
N-11
N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
CS
SCLK
DIN
DOUT
Pin Configurations (continued)
Figure 6. Transmission of More than 16 Bits to the MAX7317
10
Maxim Integrated
MAX7317
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