參數(shù)資料
型號(hào): MAX7359EWA+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA25
封裝: 2.31 X 2.31 MM, ROHS COMPLIANT, WLP-25
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 176K
代理商: MAX7359EWA+
MAX7359
2-Wire Interfaced Low-EMI
Key Switch Controller/GPO
6
_______________________________________________________________________________________
Detailed Description
The MAX7359 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events are presented
in a 16-byte FIFO. Key-switch functionality can be traded
to provide up to six open-drain logic outputs.
The MAX7359 features an automatic sleep mode and
automatic wakeup that further reduce supply current con-
sumption. The MAX7359 can be configured to enter sleep
mode after a programmable time following a key event.
The FIFO content is maintained during sleep mode and
can be read in sleep mode. The MAX7359 does not enter
autosleep when a key is held down. The autowake feature
takes the MAX7359 out of sleep mode following a key-
press event. Autosleep and autowake can be disabled.
Interrupt requests can be configured to be issued on a
programmable number of FIFO entries, or can be set
to a period of time to prevent overloading the micro-
processor with too many interrupts. The key-switch sta-
tus can be checked at any time by reading the
key-switch FIFO. A 1-byte read access returns both the
next key-event in the FIFO (if there is one) and the
FIFO status, so it is easy to operate the MAX7359 by
polling. If the INT pin is not required, it can be config-
ured as an open-drain general-purpose output (GPO)
capable of driving an LED.
If the application requires fewer keys to be scanned, up
to six of the key-switch outputs can be configured as
open-drain GPOs capable of driving LEDs. For each
key-switch output used as a GPO, the number of key
switches that can be scanned is reduced by eight.
Pin Description
PIN
TQFN
WLP
NAME
FUNCTION
1A1
ROW2
Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.
2A2
ROW3
Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
3A3
COL3/PORT3
Column Output to Key Matrix or GPO. Leave COL3/PORT3 unconnected if unused.
4B3
COL4/PORT4
Column Output to Key Matrix or GPO. Leave COL4/PORT4 unconnected if unused.
5A4
ROW4
Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.
6A5
ROW5
Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.
7B5
ROW6
Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.
8B4
ROW7
Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
9C5
COL6/PORT6
Column Output to Key Matrix or GPO. Leave COL6/PORT6 unconnected if unused.
10
C4
COL5/PORT5
Column Output to Key Matrix or GPO. Leave COL5/PORT5 unconnected if unused.
11
D5
COL2/PORT2
Column Output to Key Matrix or GPO. Leave COL2/PORT2 unconnected if unused.
12
E5
COL1
Column Output to Key Matrix. Leave COL1 unconnected if unused.
13
E4
COL0
Column Output to Key Matrix. Leave COL0 unconnected if unused.
14
D4
I.C.
Internally Connected. Connect to GND for normal operation.
15
D3
GND
Ground
16
E3
AD0
Adddress Input. ADO selects up to four device slave addresses (Table 10).
17
E2
SDA
I2C-Compatible, Serial-Data I/O
18
D2
SCL
I2C-Compatible, Serial-Clock Input
19
E1
INT
Active-Low Interrupt Output. INT is open drain.
20
D1
VCC
Positive Supply Voltage. Bypass VCC to GND with a 0.047F or higher ceramic capacitor.
21
C2, C3
N.C.
No Connection. Not internally connected.
22
C1
COL7/PORT7
Column Output to Key Matrix or GPO. Leave COL7/PORT7 unconnected is unused.
23
B2
ROW0
Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.
24
B1
ROW1
Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.
——
EP
Exposed Pad (TQFN only). EP internally is connected to GND. Connect EP to a ground plane
to increase thermal performance.
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