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Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Display Memory Mode Register (DMM)
Write address = 04H, read address = 84H.
Read/write access: unrestricted.
To write to this register, the following condition must be
met:
DMM[2] = 0, the display memory is not in the process
of being cleared.
BIT
DEFAULT
FUNCTION
7
0
Don’t Care
60
Operation Mode Selection
0 = 16-bit operation mode
The 16-bit operation mode increases the speed at which the display memory can be updated.
When writing to the display memory, the attribute byte is not entered through the SPI-compatible
interface. It is entered automatically by copying DMM[5:3] to a character’s attribute byte when a
new character is written, thus reducing the number of SPI write operations per character from two to
one (Figure 19). When in this mode, all characters written to the display memory have the same
attribute byte. This mode is useful because successive characters commonly have the same
attribute. This mode is distinct from the 8-bit operation mode where a character attribute byte must
be written each time a character address byte is written to the display memory (see Table 5). When
reading data from the display memory, both the Character Address byte and Character Attribute
byte are transferred with the SPI-compatible interface (Figure 18).
1 = 8-bit operation mode
The 8-bit operation mode provides maximum flexibility when writing characters to the display
memory. This mode enables writing individual Character Attribute bytes for each character (see
Table 5). When writing to the display memory, DMAH[1] = 0 directs the data to the Character
Address byte and DMAH[1] = 1 directs the Character Attributes byte to the data. This mode is
distinct from the 16-bit operation mode where the attribute bits are automatically copied from
DMM[5:3] when a character is written.
50
Local Background Control Bit, LBC (see Table 4)
Applies to characters written in 16-bit operating mode.
0 = Sets the background pixels of the character to the video input (VIN) when in external sync
mode.
1 = Sets the background pixels of the character to the background mode brightness level defined
by VM1[6:4] in external or internal sync mode.
Note: In internal sync mode, the local background control bit behaves as if it is set to 1.
40
Blink Bit, BLK
Applies to characters written in 16-bit operating mode.
0 = Blinking off
1 = Blinking on
Note: Blinking rate and blinking duty cycle data in the Video Mode 1 (VM1) register are used for
blinking control.
In external sync mode: when the character is not displayed, VIN is displayed.
In internal sync mode: when the character is not displayed, background mode brightness is
displayed (see VM1[6:4]).
30
Invert Bit, INV
Applies to characters written in 16-bit operating mode (see Figure 24).
0 = Normal (white pixels display white, black pixels display black)
1 = Invert (white pixels display black, black pixels display white)
MAX7456
28
Maxim Integrated