參數(shù)資料
型號(hào): MAX9156EXT-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 通用總線(xiàn)功能
英文描述: Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package
中文描述: PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO6
封裝: SC-70, 6 PIN
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 149K
代理商: MAX9156EXT-T
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9156 is a 200Mbps LVDS translator intended
for high-speed, point-to-point, low-power applications.
The MAX9156 accepts differential LVPECL inputs and
produces an LVDS output. The input voltage range
includes signals from GND up to V
CC
, allowing interop-
eration with 3.3V LVPECL devices.
The MAX9156 provides a high output when the inputs
are open. See Table 1.
M
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
_______________________________________________________________________________________
5
400
450
500
550
600
650
700
750
800
-40
-15
10
35
60
85
TRANSITION TIME
VS.
TEMPERATURE
M
TEMPERATURE (
°
C)
T
t
TLH
, t
THL
0
200
100
400
300
500
600
25
150
DIFFERENTIAL OUTPUT VOLTAGE
VS.
LOAD RESISTOR
M
LOAD RESISTOR (
)
D
75
50
100
125
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, R
L
= 100
±1%, C
L
= 10pF,
|
V
ID
|
= 0.2V, V
CM
= 1.2V, T
A
= +25
°
C, unless otherwise noted. Signal generator output:
frequency = 100MHz, 50% duty cycle, R
O
= 50
, t
R
= 1.5ns, and t
F
= 1.5ns (0% to 100%), unless otherwise noted.)
Pin Description
PIN
1
2
3
NAME
OUT-
GND
IN-
FUNCTION
Inverting LVDS Output
Ground
Inverting LVPECL-Compatible Input
4
IN+
Noninverting LVPECL-Compatible
Input
5
V
CC
Power Supply. Bypass V
CC
to GND
with a 0.01μF ceramic capacitor.
6
OUT+
Noninverting LVDS Output
INPUT, V
ID
> 50mV
< -50mV
50mV
>
V
ID
>
-50mV
Open
OUTPUT, V
OD
High
Low
Indeterminate
High
Note:
V
ID
= (IN+ - IN-), V
OD
= (OUT+ - OUT-)
High = 450mV
V
OD
250mV
Low = -250mV
V
OD
-450mV
Table 1. Function Table (Figure 2)
相關(guān)PDF資料
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MAX9156 Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package
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