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參數(shù)資料
| 型號(hào)： | MAX9163ESA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Bus LVDS 3.3V Single Transceiver |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | 0.150 INCH, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MAX9163ESA |
M
Bus LVDS 3.3V Single Transceiver
_______________________________________________________________________________________
9
For example, if C
O
= 2.5pF/in, C
L
= 10pF, N = 18, L =
18in, and Z
DF-unloaded
= 120
, the loaded differential
impedance is:
where Z
DF-loaded
= 54
In this example, capacitive loading reduces the charac-
teristic impedance from 120
to 54
. The load seen by
a driver located on a card in the middle of the bus is
27
because the driver sees two 54
terminations in
parallel. A typical LVDS driver (rated for a 100
load)
would not develop a large enough differential signal to
be detected reliably by an LVDS receiver.
The MAX9163 BLVDS driver is designed and specified
to drive a 27
load to differential voltage levels of
180mV to 360mV. A standard LVDS receiver is able to
detect this level of differential signal.
Short extensions off the bus, called stubs, contribute to
capacitive loading. Keep stubs less than 1in for a good
balance between ease of component placement and
good signal integrity.
The MAX9163 driver outputs are current-source drivers
and drive larger differential signal levels into resistances
higher than 27
and smaller levels into resistances lower
than 27
(see the
Typical Operating Characteristics
curves). To keep loading from reducing bus impedance
below the rated 27
load, PC board traces can be
designed for higher unloaded characteristic impedances.
Power-On Reset
The power-on reset voltage of the MAX9163 is typically
2.2V. When the supply falls below this voltage, the
device is disabled and the outputs (DO+/RO+, DO-/RO-,
and ROUT) are high impedance.
Applications Information
Power-Supply Bypassing
Bypass V
CC
with high-frequency, surface-mount
ceramic 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Termination
In the example in the
Effects of Capacitive Loading
section, the loaded differential impedance of the bus is
reduced to 54
. Because the bus can be driven from
any card position, it must be terminated at each end. A
parallel termination of 54
at each end of the bus
placed across the traces provides a proper termination.
The total load seen by the driver is 27
.
In a multidrop bus where the driver is at one end and
receivers are connected at regular intervals along the
bus, the bus has lowered impedance due to capacitive
loading. Assuming the same impedance as calculated
in the multidrop example (54
), the multidrop bus can
be terminated with a single, parallel-connected 54
resistor at the far end of the driver. Only a single resis-
tor is required because the driver sees one 54
differ-
ential trace. The signal swings are larger with a 54
load. In general, parallel terminate each end of the bus
with a resistor matching the differential impedance of
the bus (taking into account any reduced impedance
due to loading).
Traces, Cables, and Connectors
The characteristics of differential input and output con-
nections affect the performance of the device. Use con-
trolled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the conductors within a differential pair.
Excessive skew can result in a degradation of magnetic
field cancellation.
Maintain the distance between conductors within a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Board Layout
For BLVDS applications, a four-layer PC board with
separate power, ground, BLVDS, LVDS, and logic
signal layers is recommended. Separate the LVTTL/
LVCMOS and BLVDS signals to prevent coupling.
Z
x
pF
pF
x
pF
in
DF loaded
=
+
[
]
120
2 5
.
18
(
10
18
/ (2 5
/
))
V
CC
DO+/RI+
DO-/RI-
ROUT
2.5
μ
A
GND
5
μ
A
35mV
MAX9163
Figure 6. Input Fail-Safe Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9163 | Bus LVDS 3.3V Single Transceiver |
| MAX9169-MAX9170 | 4-Port LVDS and LVTTL-to-LVDS Repeaters |
| MAX9169ESE | 4-Port LVDS and LVTTL-to-LVDS Repeaters |
| MAX9169EUE | 4-Port LVDS and LVTTL-to-LVDS Repeaters |
| MAX9170ESE | 4-Port LVDS and LVTTL-to-LVDS Repeaters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9163ESA+ | 功能描述:LVDS 接口集成電路 Bus LVDS 3.3V Single Transceiver RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9163ESA+T | 功能描述:LVDS 接口集成電路 Bus LVDS 3.3V Single Transceiver RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9163ESA-T | 功能描述:LVDS 接口集成電路 Bus LVDS 3.3V Single Transceiver RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9164 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V Single LVDS Driver/Receiver |
| MAX9164ESD | 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:3.3V SINGLE LVDS DRIVER/RECEIVER - Rail/Tube |
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