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參數(shù)資料
| 型號： | MAX9214EUM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER PROG 48TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 3 |
| 輸出數(shù)： | 21 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
12
______________________________________________________________________________________
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 13) is:
C = - (4 x tB x DSV)/(ln (1 - D) x (RT + RO)) (Eq 3)
Fail-Safe
The MAX9210/MAX9214/MAX9220/MAX9222 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the correspond-
ing LVDS input is open, undriven and shorted, or
undriven and parallel terminated. The fail-safe on the
LVDS clock input drives all outputs low. Fail-safe does
not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42k
Ω (min) to provide biasing for AC-coupling (Figure 1).
A frequency-detection circuit on the clock input detects
when the input is not switching, or is switching at low
frequency. In this case, all outputs are driven low. To
prevent switching due to noise when the clock input is
not driven, bias the clock input to differential +15mV by
connecting a 10k
Ω ±1% pullup resistor between the
noninverting input and VCC, and a 10k
Ω ±1% pulldown
resistor between the inverting input and ground. These
bias resistors, along with the 100
Ω ±1% tolerance ter-
mination resistor, provide +15mV of differential input.
However, the +15mV bias causes degradation of
RSKM proportional to the slew rate of the clock input.
For example, if the clock transitions 250mV in 500ps,
the slew rate of 0.5mV/ps reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC balanced mode, the input fail-
safe circuit drives the corresponding outputs low and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to VCC using a 10k
Ω resistor, and pull the nonin-
verting input down to ground using a 10k
Ω resistor. Do
not connect a termination resistor. The pullup and pull-
down resistors drive the corresponding outputs low and
prevent switching due to noise.
(7 + 2):1
1:(9 - 2)
7
100
Ω
(7 + 2):1
1:(9 - 2)
7
100
Ω
(7 + 2):1
1:(9 - 2)
7
100
Ω
PLL
100
Ω
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX9215ETM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balanced 21-Bit Serializers |
| MAX9215EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balanced 21-Bit Serializers |
| MAX9216 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9216ETM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9216EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
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