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參數資料
| 型號： | MAX9242_07 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| 中文描述： | 21與可編程擴頻和直流平衡位解串器 |
| 文件頁數： | 17/22頁 |
| 文件大小： | 306K |
| 代理商： | MAX9242_07 |
M
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________
17
R
T
is required to match the transmission line impedance
(usually 100
Ω
) and R
O
is determined by the LVDS dri-
ver design (the minimum differential output resistance of
78
Ω
for the MAX9209/MAX9213 serializers is used in
the following example). This condition leaves the capac-
itor selection to change the system time constant.
In the following example, the capacitor value for a 2%
droop is calculated. Jitter due to this droop is then cal-
culated assuming a 1ns transition time:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 1)
where:
C = AC-coupling capacitor (F)
t
B
= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
T
= termination resistor (
Ω
)
R
O
= output resistance (
Ω
)
Equation 1 is for two series capacitors (Figure 19). The bit
time (t
B
) is the period of the parallel clock divided by 9.
The DSV is 10. See equation 3 for four series capacitors
(Figure 20).
The capacitor for 2% maximum droop at 16MHz parallel
rate clock is:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
))
C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100
Ω
+ 78
Ω
))
C = 0.038μF
Jitter due to droop is proportional to the droop and
transition time:
t
J
= t
T
x D (Eq 2)
where:
t
J
= jitter (s)
t
T
= transition time (s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
t
J
= 1ns x 0.02
t
J
= 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
7:1
1:7 FIFO
7
7
100
Ω
7:1
1:7 FIFO
7
7
100
Ω
7:1
1:7 FIFO
7
7
100
Ω
PLL
PLL1 +
SSPLL
100
Ω
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
R
O
R
T
相關PDF資料 |
PDF描述 |
|---|---|
| MAX9242EUM | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9242GUM | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9244GUM | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9246EUM | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MAX9242EUM | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數量:4 接收機數量:4 數據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9242EUM/V+ | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242EUM/V+T | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242EUM+ | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242EUM+D | 制造商:Maxim Integrated Products 功能描述:21-BIT DC-BALANCED LVDS DESERIALIZERS WITH SPREAD SPECTRUM - Rail/Tube |
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