參數(shù)資料
型號(hào): MAX9316
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125
中文描述: 1:5差分LVPECL/LVECL/HSTL時(shí)鐘和數(shù)據(jù)驅(qū)動(dòng)器
文件頁(yè)數(shù): 4/12頁(yè)
文件大小: 214K
代理商: MAX9316
M
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
4
_______________________________________________________________________________________
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at T
A
= +25
°
C and guaranteed by design over the full operating temperature range.
Note 4:
Use V
BB
only for inputs that are on the same device as the V
BB
reference.
Note 5:
All pins are open except V
CC
and V
EE
.
Note 6:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 7:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 8:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9:
Device jitter added to a jitter-free input signal.
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= +3.0V to +3.8V, outputs are loaded with 50
±1% to V
CC
- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), SEL = high or low,
EN
= low, V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to 3V, unless
otherwise noted. Typical values are at V
CC
- V
EE
= +3.3V.) (Notes 1, 6)
-40
°
C
TYP
+25
°
C
TYP
+85
°
C
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CLK to Q_ Delay
(Differential)
t
PLHD1
,
t
PHLD1
Figure 2
290
400
310
440
300
520
ps
SCLK to Q_ Delay
t
PLHD3
,
t
PHLD3
V
IL
= V
CC
- 1.55V,
V
IH
= V
CC
- 1.09V,
Figure 3
290
400
310
440
300
520
ps
Output-to-Output
Skew (Note 7)
t
SKOO
5
30
20
40
20
50
ps
Part-to-Part Skew
(Note 8)
t
SKPP
110
130
220
ps
Added Random
Jitter (Note 9)
t
RJ
f
IN
= 1.5GHz clock
0.8
1.2
0.8
1.2
0.8
1.2
p s
( RM S
Added
Deterministic Jitter
(Note 9)
t
DJ
1.5Gbps 2E
23
-1
PRBS pattern
50
70
50
70
50
70
ps (p-p)
Switching
Frequency
f
MAX
( V
OH
- V
OL
)
400m V
Figure 2
1.5
1.5
1.5
GHz
Output Rise/Fall
Time (20% to 80%)
t
R
, t
F
Figure 2
80
120
90
130
90
145
ps
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