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參數(shù)資料
| 型號(hào)： | MAX9320BEUA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver |
| 中文描述： | LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 120K |
| 代理商： | MAX9320BEUA |
M
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
6
_______________________________________________________________________________________
Detailed Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. For interfacing
to differential PECL and LVPECL signals, this device
operates over a +3.0V to +5.5V supply range, allowing
high-performance clock and data distribution in sys-
tems with a nominal 3.3V or 5V supply. For differential
ECL and LVECL operation, this device operates from a
-3.0V to -5.5V supply.
Inputs
The maximum magnitude of the differential input from D
to
D
is 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input,
D
, is biased with a 50k
pullup to
V
CC
and a 100k
pulldown to V
EE
. The noninverting
input, D, is biased with an 80k
pullup to V
CC
and a
60k
pulldown to V
EE
.
Specifications for the high and low voltages of the dif-
ferential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously (V
ILD
cannot
be higher than V
IHD
).
Outputs
Output levels are referenced to V
CC
and are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the V
CC
supply. With V
CC
connected to a posi-
tive supply and V
EE
connected to GND, the outputs are
PECL/LVPECL. The outputs are ECL/LVECL when V
CC
is connected to GND and V
EE
is connected to a nega-
tive supply.
A differential input of at least ±100mV switches the out-
puts to the V
OH
and V
OL
levels specified in the
DC
Electrical Characteristics
table.
Applications Information
Supply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1μF and 0.01μF capacitors in parallel as
close to the device as possible, with the 0.01μF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance.
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9320B. Connect each signal of a differ-
ential input or output to a 50
characteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50
characteristic impedance through connectors and
across cables. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output Termination
Terminate outputs through 50
to V
CC
- 2V or use an
equivalent Thevenin termination. Terminate both out-
puts and use the same termination on each for the low-
est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out-
puts. For example, if Q0 is used as a single-ended out-
put, terminate both Q0 and
Q0.
Chip Information
TRANSISTOR COUNT: 182
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