- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383541 > MAX9322 (Maxim Integrated Products, Inc.) LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | MAX9322 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver |
| 中文描述： | LVECL/LVPECL 1:15差分、除1/除2、時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | MAX9322 |
M
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS Outputs
_______________________________________________________________________________________
7
Detailed Description
The MAX9310 is a low-skew 1:5 differential driver with
two selectable LVPECL inputs and LVDS outputs,
designed for clock distribution applications. The select-
ed clock accepts a differential input signal and repro-
duces it on five separate differential LVDS outputs. The
inputs are biased with internal resistors such that the
output is differential low when inputs are open. The out-
put drivers are guaranteed to operate at frequencies up
to 1.0GHz with LVDS output levels conforming to the
EIA/TIA-644 standard.
The MAX9310 is designed for 2.375V to 2.625V opera-
tion in systems with a nominal 2.5V supply.
Differential LVPECL Input
The MAX9310 has two input differential pairs that
accept differential LVPECL/HSTL inputs. Each differen-
tial input pair has to be independently terminated. A
select pin (CLKSEL) is used to activate the desired
input. The maximum magnitude of the differential signal
applied to the input is V
CC
. Specifications for the high
and low voltages of a differential input (V
IHD
and V
ILD
)
and the differential input voltage (V
IHD
- V
ILD
) apply
simultaneously.
Synchronous Enable
The MAX9310 is synchronously enabled and disabled
with outputs in a differential low state to eliminate short-
ened clock pulses.
EN
is connected to the input of an
edge-triggered D flip-flop. After power-up, drive
EN
low
and toggle the selected clock input to enable the out-
puts. The outputs are enabled on the falling edge of the
selected clock input after
EN
goes low. The outputs are
set to a differential low state on the falling edge of the
selected clock input after
EN
goes high (Figure 2).
Input Bias Resistors
Internal biasing resistors ensure a (differential) output
low condition in the event that the inputs are not con-
nected. The inverting input (
CLK_
) is biased with a
75k
pulldown to GND and a 75k
pullup to V
CC
. The
noninverting input (CLK_) is biased with a 75k
pull-
down to GND.
Differential LVDS Output
The LVDS outputs must be terminated with 100
across Q_ and
Q_,
as shown in the
Typical Application
Circuit
. The outputs are short-circuit protected.
Applications Information
Supply Bypassing
Bypass each V
CC
to GND with high-frequency surface-
mount ceramic 0.1μF and 0.01μF capacitors in parallel
as close to the device as possible, with the 0.01μF
capacitor closest to the device. Use multiple parallel
vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9310. Connect high-frequency input
and output signals to 50
characteristic impedance
traces. Minimize the number of vias to prevent imped-
ance discontinuities. Reduce reflections by maintaining
the 50
characteristic impedance through cables and
connectors. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output Termination
Terminate the outputs with 100
across Q_ and
Q_,
as
shown in the
Typical Application Circuit
.
Chip Information
TRANSISTOR COUNT: 716
PROCESS: Bipolar
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9323 | One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver |
| MAX9324 | One-to-Five LVPECL/LVCMOS Output Clock and Data Driver |
| MAX9325 | 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver |
| MAX9326 | 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver |
| MAX9382EVKIT | Evaluation Kit for the MAX9382/MAX9383 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9322ECY+ | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL DIVIDE-BY-1/DIVIDE-BY-2 CLOCK DRVR 52TQFP - Rail/Tube |
| MAX9322ECY+D | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX9322ECY+T | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL DIVIDE-BY-1/DIVIDE-BY-2 CLOCK DRVR 52TQFP - Tape and Reel |
| MAX9322ECY+TD | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| MAX9322ECY-D | 功能描述:通信集成電路 - 若干 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。