參數(shù)資料
型號(hào): MAX9471ETP+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/13頁(yè)
文件大小: 0K
描述: IC MULTI-PURPOSE CLK GEN 20-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘發(fā)生器
PLL:
輸入: LVCMOS,晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 200MHz
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9471/MAX9472
Multiple-Output Clock Generators with
Dual PLLs and OTP
4
_______________________________________________________________________________________
SERIAL-INTERFACE TIMING CHARACTERISTICS (MAX9471)
(VDD = VDDA = +3.3V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock
fSCL
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
Hold Time, Repeated START
Condition
tHD,STA
0.6
s
Repeated START Condition
Setup Time
tSU,STA
0.6
s
STOP Condition Setup Time
tSU,STO
0.6
s
Data Hold Time
tHD,DAT
(Note 4)
15
900
ns
Data Setup Time
tSU,DAT
100
ns
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.7
s
Rise Time of SDA and SCL,
Receiving
tR
(Notes 3, 5)
20 +
0.1Cb
300
ns
Fall Time of SDA and SCL,
Receiving
tF
(Notes 3, 5)
20 +
0.1Cb
300
ns
Fall Time of SDA, Transmitting
tF,TX
(Notes 3, 6)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 3, 7)
0
50
ns
Capacitive Load for Each
Bus Line
Cb
(Note 3)
400
pF
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level
voltage.
Note 3: Guaranteed by design.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD.
Note 6: Bus sink current is less than 6mA. Cb is the total capacitance of one bus line in pF. tR and tF are measured between
0.3 x VDD and 0.7 x VDD.
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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