參數(shù)資料
型號(hào)： MAX9472
廠商： Maxim Integrated Products, Inc.
英文描述： Multiple-Output Clock Generators with Dual PLLs and OTP
中文描述： 多輸出時(shí)鐘發(fā)生器，提供雙PLL和OTP
文件頁(yè)數(shù)： 4/13頁(yè)
文件大?。?/td> 3400K
代理商： MAX9472
M
Multiple-Output Clock Generators with
Dual PLLs and OTP
4
_______________________________________________________________________________________
SERIAL-INTERFACE TIMING CHARACTERISTICS (MAX9471)
(V
DD
= V
DDA
= +3.3V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER
SYMBOL
f
SCL
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
Serial Clock
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3
μs
Hold Time, Repeated START
Condition
t
HD,STA
0.6
μs
Repeated START Condition
Setup Time
t
SU,STA
0.6
μs
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t
SU,STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
0.6
15
100
1.3
0.7
μs
ns
ns
μs
μs
(Note 4)
900
Rise Time of SDA and SCL,
Receiving
t
R
(Notes 3, 5)
20 +
0.1C
b
300
ns
Fall Time of SDA and SCL,
Receiving
t
F
(Notes 3, 5)
20 +
0.1C
b
300
ns
Fall Time of SDA, Transmitting
t
F,TX
(Notes 3, 6)
20 +
0.1C
b
0
250
ns
Pulse Width of Spike Suppressed
t
SP
(Notes 3, 7)
50
ns
Capacitive Load for Each
Bus Line
C
b
(Note 3)
400
pF
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level
voltage.
Note 3:
Guaranteed by design.
Note 4:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 5:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 6:
Bus sink current is less than 6mA. C
b
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between
0.3 x V
DD
and 0.7 x V
DD
.
Note 7:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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