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參數(shù)資料
| 型號： | MAX9472 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Multiple-Output Clock Generators with Dual PLLs and OTP |
| 中文描述： | 多輸出時鐘發(fā)生器，提供雙PLL和OTP |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 3400K |
| 代理商： | MAX9472 |
Device Address
The default I
2
C address for the MAX9471 is factory set to
1100111. Contact factory for different addresses.
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. The active master signals the beginning of a
transmission with a START (S) condition by transitioning
SDA from high to low while SCL is high. When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Data Transfer and ACK
Following the START condition, each SCL clock pulse
transfers 1 bit. Between a START and a STOP, multiple
bits are transferred on the 2-wire bus. The first 7 bits are
for the device address. Bit 8 indicates the writing (low)
or reading (high) operation (R/
W
). Bit 9 is the ACK for
the address and operation type. The next 8 bits (bit 10
to bit 17) form the content byte. The next bit, bit 18, is
the ACK for the content byte. The master always trans-
fers the first 8 bits (address + R/
W
). The slave
(MAX9471) may receive a content byte from the bus or
transfer a content byte to the bus. The ACK bits are
transmitted by the address or content recipient. A low-
ACK bit indicates a successful transfer; otherwise, a
high-ACK bit indicates an unsuccessful transfer. More
content bytes can be continuously transferred until the
master sends a STOP. For the MAX9471 data writing,
after the 9 bits with the slave ID, R/
W
, and ACK, 1 data
byte is sent to the MAX9471 from the master. Figure 4
shows the structure of the data transfer. Figure 5 shows
CLK_ rise and fall times.
M
Multiple-Output Clock Generators with
Dual PLLs and OTP
_______________________________________________________________________________________
9
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
Figure 3. START and STOP Diagram
A
A
P
A
W
S
SLAVE ADDRESS
MASTER-WRITE DATA STRUCTURE
MASTER-READ DATA STRUCTURE
DATA
A
A
P
A
R
S
SLAVE ADDRESS
DATA
MASTER TRANSFERS TO SLAVE
SLAVE TRANSFERS TO MASTER
A = ACK; A = 0: SUCCESSFUL, A = 1: UNSUCCESSFUL
S = START CONDITION
P = STOP CONDITION
Figure 4. Serial-Interface Data Structure
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| MAX9476EUG-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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