參數(shù)資料
型號: MAX9650ATA+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/13頁
文件大小: 0K
描述: IC OPAMP VCOM DRIVE 8-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
應(yīng)用: TFT-LCD 面板:VCOM 驅(qū)動器
輸出類型: 滿擺幅
電路數(shù): 1
-3db帶寬: 35MHz
轉(zhuǎn)換速率: 40 V/µs
電流 - 電源: 3.7mA
電流 - 輸出 / 通道: 1.3A
電壓 - 電源,單路/雙路(±): 9 V ~ 20 V,±4.5 V ~ 10 V
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 帶卷 (TR)
Detailed Description
The MAX9650/MAX9651 operational rail-to-rail
input/output amplifiers hold the VCOM voltage stable
while providing the ability to source and sink a high cur-
rent quickly (1.3A) into a capacitive load such as the
backplane of a TFT-LCD panel.
Thermal Shutdown
with Temperature Hysteresis
The MAX9650/MAX9651 are capable of high output
currents and feature thermal-shutdown protection with
temperature hysteresis. When the die temperature
reaches +170°C, the device shuts down. When the die
cools down by 15°C, the device turns on again. In a
TFT-LCD application, the duty cycle is very low. Even
with high values of voltage and current, the power dissi-
pation is low and the chip does not shut down.
High-Current VCOM Drive Op Amps
for TFT LCDs
Maxim Integrated
5
MAX9650/MAX9651
Pin Description
PIN
MAX9650
SOT23
MAX-EP,
TDFN-EP
MAX9651
(MAX-EP,
TDFN-EP)
NAME
FUNCTION
16
1
OUTA
VCOM Output A
24
4
GND
Ground
33
3
INA+
Positive Input A
42
2
INA-
Negative Input A
57
8
VDD
Positive-Supply Input. Bypass VDD to GND with a 0.1F capacitor as close as
possible to the device.
——
5
INB+
Positive Input B
——
6
INB-
Negative Input B
——
7
OUTB
VCOM Output B
1, 5, 8
N.C.
No Connection. Not internally connected.
——
—EP
Exposed Pad (
μMAX and TDFN Only). EP is internally connected to GND. Connect EP
to GND.
IN_+
IN_-
GND
OUT_
VDD
LCD VCOM LOAD
19V
SUPPLY
VREF
*10
μF and 0.1μF CAPACITORS AS CLOSE AS POSSIBLE TO THE PIN.
**(RS = RGEN) x CLCD x 6 < 2
μs, WHERE RGEN = GENERATOR SOURCE IMPEDANCE.
MAX9650
*C2 = 0.1
μF
*C1 = 10
μF
19V
SUPPLY
VOUT_
CLCD =
0.1
μF
RS =
2.2
Ω
**0V TO 2.2V
AT 50kHz
Figure 1. Settling Time Test Circuit
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